SYSTEM ON A CHIP WITH CLOCK CIRCUITS
An embodiment of a system on a chip includes a reference clock circuit configured to produce a reference clock signal, a first clock circuit configured to produce a first clock signal, and adjustment circuitry. The adjustment circuitry is configured to make a determination of whether a characteristic of the reference clock signal compares unfavorably with a characteristic of the first clock signal, and when the characteristic of the reference clock signal compares unfavorably with the characteristic of the first clock signal, to adjust a parameter of the first clock circuit that results in tuning the first clock signal.
1 . A system on a chip (SOC) comprising:
a processing module;
read only memory (ROM) coupled to the processing module;
random access memory (RAM) coupled to the processing module;
a reference clock circuit that, when enabled, produces a reference clock signal; and
a first clock circuit coupled to produce a clock signal, wherein the first clock circuit, from time-to-time, tunes the clock signal based on the reference clock signal, wherein the reference clock circuit is enabled for the from time-to-time, wherein the reference clock signal is more accurate than the clock signal, and wherein the processing module utilizes the clock signal.
2 . The SOC of claim 1 , wherein the first clock circuit comprises at least one of:
a ring oscillator circuit;
an inductor-capacitor resonating oscillator circuit; and
a resistor-capacitor oscillator circuit.
3 . The SOC of claim 1 , wherein the reference clock circuit comprises at least one of:
a crystal oscillator circuit;
a phase locked loop; and
a counter based oscillator circuit.
4 . The SOC of claim 1 , wherein the first clock circuit, from time-to-time, tunes the clock signal based on the reference clock signal by:
comparing phase of the reference clock signal with phase of the clock signal;
when the phase of the reference clock signal compares unfavorably with the phase of the clock signal, adjusting a parameter of the first clock circuit.
5 . The SOC of claim 4 , wherein the parameter of the first clock circuit comprises at least one of:
a biasing level;
a component value; and
a supply voltage level.
6 . The SOC of claim 1 , wherein the first clock circuit, from time-to-time, tunes the clock signal based on the reference clock signal by:
comparing frequency of the reference clock signal with frequency of the clock signal;
when the frequency of the reference clock signal compares unfavorably with the frequency of the clock signal, adjusting a parameter of the first clock circuit.
7 . A system on a chip (SOC) comprising:
a reference clock circuit configured to produce a reference clock signal;
a first clock circuit coupled to the reference clock circuit, and configured to produce a first clock signal; and
adjustment circuitry coupled to receive the reference clock signal and the first clock signal, wherein the adjustment circuitry is configured to make a determination of whether a characteristic of the reference clock signal compares unfavorably with a characteristic of the first clock signal, and when the characteristic of the reference clock signal compares unfavorably with the characteristic of the first clock signal, to adjust a parameter of the first clock circuit that results in tuning the first clock signal.
8 . The SOC of claim 7 , wherein the reference clock signal is more accurate than the first clock signal.
9 . The SOC of claim 7 , wherein the reference clock circuit produces the reference clock signal when enabled, and wherein the SOC further comprises:
circuitry configured to periodically enable the reference clock circuit for a period of time so that the reference clock circuit may produce the reference clock signal and the first clock circuit may tune the first clock signal, and to disable the reference clock circuit after the period of time.
10 . The SOC of claim 7 , wherein the adjustment circuitry is configured to make the determination by comparing a first phase of the first clock signal with a second phase of the reference clock signal, and to make the determination that the characteristic of the reference clock signal compares unfavorably with the characteristic of the first clock signal when the first clock signal and the second clock signal are out of phase.
11 . The SOC of claim 7 , wherein the adjustment circuitry is configured to make the determination by comparing a first frequency of the first clock signal with a second frequency of the reference clock signal, and to make the determination that the characteristic of the reference clock signal compares unfavorably with the characteristic of the first clock signal when the first clock signal and the second clock signal are out of frequency step.
12 . The SOC of claim 7 , wherein the adjustment circuitry comprises:
a first counter configured to count a first number of cycles of the first clock signal;
a second counter configured to count a second number of cycles of the second clock signal; and
comparison circuitry configured to compare the first number with the second number, wherein the determination is made that the characteristic of the second clock signal compares unfavorably with the characteristic of the first clock signal when the first number and the second number do not match.
13 . A method performed on a system on a chip (SOC) for producing a clock signal, the method comprising the steps of:
producing, by a first clock circuit of the SOC, a first clock signal;
producing, by a reference clock circuit of the SOC, a second clock signal that corresponds to a reference clock signal;
making a determination of whether a characteristic of the second clock signal compares unfavorably with a characteristic of the first clock signal; and
when the characteristic of the second clock signal compares unfavorably with the characteristic of the first clock signal, adjusting a parameter of the first clock circuit that results in tuning the first clock signal.
14 . The method of claim 13 , wherein the reference clock circuit produces the second clock signal when enabled, and the method further comprises the steps of:
periodically enabling the reference clock circuit for a period of time so that the reference clock circuit may produce the second clock signal and the first clock circuit may tune the first clock signal; and
disabling the reference clock circuit after the period of time.
15 . The method of claim 13 , wherein the first clock circuit comprises a ring oscillator circuit, and wherein adjusting the parameter comprises adjusting a biasing level to adjust a slew rate of the ring oscillator circuit.
16 . The method of claim 13 , wherein the first clock circuit comprises a resistor-capacitor oscillator circuit, and wherein adjusting the parameter comprises adjusting a component value of the resistor-capacitor oscillator circuit.
17 . The method of claim 13 , wherein adjusting the parameter comprises adjusting a supply voltage level of the first clock circuit, and wherein lowering the supply voltage level causes the first clock signal to decrease in speed, and increasing the supply voltage level causes the first clock signal to increase in speed.
18 . The method of claim 13 , wherein making the determination comprises comparing a first phase of the first clock signal with a second phase of the second clock signal, and wherein the determination is made that the characteristic of the second clock signal compares unfavorably with the characteristic of the first clock signal when the first clock signal and the second clock signal are out of phase.
19 . The method of claim 13 , wherein making the determination comprises comparing a first frequency of the first clock signal with a second frequency of the second clock signal, and wherein the determination is made that the characteristic of the second clock signal compares unfavorably with the characteristic of the first clock signal when the first clock signal and the second clock signal are out of frequency step.
20 . The method of claim 13 , wherein making the determination comprises:
counting a first number of cycles of the first clock signal;
counting a second number of cycles of the second clock signal;
comparing the first number with the second number; and
making the determination that the characteristic of the second clock signal compares unfavorably with the characteristic of the first clock signal when the first number and the second number do not match.