Method of forming a semiconductor device featuring a gate stressor and semiconductor device
View Patent ↗A semiconductor device is formed in a semiconductor layer. A gate stack is formed over the semiconductor layer and comprises a first conductive layer and a second layer over the first layer. The first layer is more conductive and provides more stopping power to an implant than the second layer. A species is implanted into the second layer. Source/drain regions are formed in the semiconductor layer on opposing sides of the gate stack. The gate stack is heated after the step of implanting to cause the gate stack to exert stress in the semiconductor layer in a region under the gate stack.
1. A semiconductor device, comprising:
a semiconductor layer;
a gate stack over the semiconductor layer comprising:
a first layer comprising a metallic element over the semiconductor layer;
a second layer over the first layer, wherein the first layer is more conductive and provides more stopping power to an implant than the second layer;
a stressor located in the second layer within 10 nanometers of the first layer; and
source/drain regions in the semiconductor layer on opposite sides of the gate stack.
2. The semiconductor device of claim 1 , wherein the stressor adjoins the first layer.
3. The semiconductor device of claim 1 , wherein the second layer comprises polysilicon.
4. The semiconductor device of claim 1 , wherein the stressor comprises oxide.
5. The semiconductor device of claim 3 , wherein the stressor comprises oxide.
6. The semiconductor device of claim 2 , wherein the second layer comprises polysilicon.
7. The semiconductor device of claim 2 , wherein the stressor comprises oxide.
8. The device of claim 1 , wherein the second layer provides more stopping power to an oxygen implant.
9. The device of claim 8 , wherein the stressor comprises oxygen at a density of 1E23 cm −3 .
10. The device of claim 1 , wherein the metallic element comprises tantalum.
11. The device of claim 8 , wherein the no other gate stack lies between the first and second gate stacks.
12. The device of claim 1 , wherein the first gate stack further comprises a gate dielectric between the semiconductor layer and the first layer over a channel between source/drain regions.
13. A semiconductor device, comprising:
a gate stack over a semiconductor layer comprising a first layer and a second layer over the first layer, the first layer is more conductive than the second layer and the first layer comprising a metallic element and having more stopping power to an implant than the second layer, the second layer including a stressor species within 10 nm of the first layer that exerts stress in the semiconductor layer in a region under the gate stack.
14. The device of claim 13 wherein a maximum concentration of the stressor species is within 10 nm of the first layer.
15. The device of claim 14 , wherein the stressor species is oxygen.
16. The device of claim 13 , wherein the stressor species is oxygen.
17. The device of claim 13 , wherein an oxide includes the stressor species.
18. The device of claim 13 , wherein no other gate stack lies between the first and second gate stacks.
19. The device of claim 13 , wherein the metallic element comprises tantalum.