IP Library Granted Patent US 8,922,227
Granted Patent B2
US 8,922,227 · App. 13/043,075 · Granted Dec 30, 2014

Systems and methods for detecting surface charge

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Quick Facts
Patent No.
US 8,922,227
App. No.
13/043,075
Granted
Dec 30, 2014
Kind
B2
Abstract

Systems and methods are provided for detecting surface charge on a semiconductor substrate having a sensing arrangement formed thereon. An exemplary sensing system includes the semiconductor substrate having the sensing arrangement formed thereon, and a module coupled to the sensing arrangement. The module obtains a first voltage output from the sensing arrangement when a first voltage is applied to the semiconductor substrate, obtains a second voltage output from the sensing arrangement when a second voltage is applied to the semiconductor substrate, and detects electric charge on the surface of the semiconductor substrate based on a difference between the first voltage output and the second voltage output.

Claims (51)

1. A sensing system comprising:

a semiconductor substrate having a sensing arrangement formed thereon; and

a module including at least one input coupled to an output of the sensing arrangement to obtain a first signal indicative of a sensed quantity from the output of the sensing arrangement when a first substrate voltage is applied to a body of the semiconductor substrate, obtain a second signal indicative of the sensed quantity from the output of the sensing arrangement when a second substrate voltage is applied to the body of the semiconductor substrate, and detect an electric charge on a surface of the semiconductor substrate based on a difference between the first signal and the second signal that is greater than a threshold amount.

2. The sensing system of claim 1 , wherein the threshold amount corresponds to a voltage difference that is indicative of a leakage current caused by the electric charge on the surface of the semiconductor substrate, the electric charge being detected when the difference is greater than the threshold amount.

3. The sensing system of claim 1 , wherein the module further comprises:

a first voltage regulating element to provide the first substrate voltage;

a second voltage regulating element to provide the second substrate voltage; and

selection circuitry coupled to the first voltage regulating element and the second voltage regulating element, the selection circuitry having an output coupled to the semiconductor substrate, wherein the module controls the selection circuitry to apply the first substrate voltage from the first voltage regulating element to the body of the semiconductor substrate and the second substrate voltage from the second voltage regulating element to the body of the semiconductor substrate.

4. The sensing system of claim 3 , wherein the output of the selection circuitry is coupled to a substrate pad on the semiconductor substrate for biasing the body of the semiconductor substrate.

5. The sensing system of claim 1 , wherein the sensing arrangement comprises a plurality of piezoresistive elements formed on a diaphragm region of the semiconductor substrate.

6. The sensing system of claim 5 , wherein:

the plurality of piezoresistive elements are arranged as a Wheatstone bridge having a pair of output nodes;

the first signal is a first output voltage from the pair of output nodes when the first substrate voltage is applied to the body of the semiconductor substrate;

the second signal is a second output voltage from the pair of output nodes when the second substrate voltage is applied to the body of the semiconductor substrate; and

the electric charge on the surface of the semiconductor substrate is detected by the module when the difference between the first output voltage and the second output voltage is greater than the threshold amount.

7. The sensing system of claim 6 , further comprising a substrate pad on the semiconductor substrate for biasing the body of the semiconductor substrate, wherein the module includes an output coupled to the substrate pad to apply the first substrate voltage and the second substrate voltage to the body of the semiconductor substrate.

8. The sensing system of claim 5 , further comprising a substrate pad on the semiconductor substrate for biasing the body of the semiconductor substrate, wherein:

the semiconductor substrate has a first conductivity-type;

the substrate pad is formed overlying a first doped region formed in the semiconductor substrate having the first conductivity-type; and

each piezoresistive element comprises one or more doped regions having a second conductivity-type formed on the diaphragm region.

9. The sensing system of claim 1 , wherein the module indicates presence of the electric charge on the surface of the semiconductor substrate in response to detecting the electric charge on the surface of the semiconductor substrate.

10. The sensing system of claim 1 , wherein the module generates an interrupt signal in response to detecting the electric charge on the surface of the semiconductor substrate.

11. A method for operating a sensing device including a sensing arrangement formed on a semiconductor substrate, the method comprising:

applying a first substrate voltage to a body of the semiconductor substrate;

obtaining a first output indicative of a sensed quantity from the sensing arrangement while the first substrate voltage is applied to the body of the semiconductor substrate;

applying a second substrate voltage to the semiconductor substrate, the second substrate voltage being different from the first substrate voltage;

obtaining a second output indicative of the sensed quantity from the sensing arrangement while the second substrate voltage is applied to the body of the semiconductor substrate; and

identifying a charge on a surface of the semiconductor substrate when a difference between the first output and the second output is greater than a threshold amount.

12. The method of claim 11 , further comprising calibrating the sensing arrangement when the difference between the first output and the second output is less than the threshold amount.

13. The method of claim 11 , further comprising taking remedial action in response to identifying the charge on the surface of the semiconductor substrate.

14. The method of claim 11 , further comprising generating an interrupt signal in response to identifying the charge on the surface of the semiconductor substrate.

15. The method of claim 11 , wherein:

the sensing arrangement comprises a plurality of piezoresistive elements formed on the semiconductor substrate;

obtaining the first output comprises obtaining a first output voltage from the plurality of piezoresistive elements; and

obtaining the second output comprises obtaining a second output voltage from the plurality of piezoresistive elements.

16. The method of claim 15 , further comprising calibrating the sensing arrangement when the difference between the first output voltage and the second output voltage is less than the threshold amount.

17. The method of claim 16 , wherein calibrating the sensing arrangement comprises:

applying a bias voltage to the semiconductor substrate;

obtaining a third output voltage from the plurality of piezoresistive elements while the bias voltage is applied to the semiconductor substrate; and

determining a factor for converting a subsequent output voltage from the plurality of piezoresistive elements to a corresponding sensed metric value based on the third output voltage.

18. A method for operating a sensing device, the sensing device including a sensing arrangement formed on a semiconductor substrate, the method comprising:

applying a plurality of substrate voltages to a body of the semiconductor substrate, each substrate voltage of the plurality of substrate voltages being applied to the body of the semiconductor substrate at a different time, wherein a respective output signal indicative of a sensed quantity is obtained from the sensing arrangement for each substrate voltage of the plurality of substrate voltages while the respective substrate voltage is applied to the body of the semiconductor substrate, resulting in a plurality of output signals; and

detecting a surface charge condition based upon a difference among the plurality of output signals.

19. The method of claim 18 , wherein:

applying the plurality of substrate voltages comprises:

applying an initial substrate voltage to the body of the semiconductor substrate, the plurality of output signals including an initial output voltage obtained from the sensing arrangement while the initial substrate voltage is applied to the body of the semiconductor substrate; and

applying a second substrate voltage to the body of the semiconductor substrate, the plurality of output signals including a second output voltage obtained from the sensing arrangement while the second substrate voltage is applied to the body of the semiconductor substrate; and

detecting the surface charge condition comprises identifying when a difference between the second output voltage and the initial output voltage exceeds a threshold amount.

20. The method of claim 18 , the sensing arrangement comprising a plurality of piezoresistive elements formed on a diaphragm region of the semiconductor substrate, the plurality of piezoresistive elements being configured to generate a voltage output indicative of pressure applied to the sensing device, wherein the method further comprises:

obtaining an initial measured voltage output from the plurality of piezoresistive elements when the a first substrate voltage of the plurality of substrate voltages is applied to the body of the semiconductor substrate; and

obtaining a second measured voltage output from the plurality of piezoresistive elements when a second substrate voltage of the plurality of substrate voltages is applied to the body of the semiconductor substrate, the surface charge condition being detected when a difference between the second measured voltage output and the initial measured voltage output exceeds a threshold amount.

Assignments (31)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
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From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
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MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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PATENT RELEASE Recorded Dec 21, 2015
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PATENT RELEASE Recorded Dec 21, 2015
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SECURITY AGREEMENT Recorded Nov 6, 2013
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To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
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SECURITY AGREEMENT Recorded Jan 31, 2012
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To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jan 31, 2012
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To: CITIBANK, N.A., AS COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2011
From: DAWSON, CHAD S.; GROTE, BERNHARD H.; PARK, WOO TAE
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