Non-volatile memory (NVM) with imminent error prediction
View Patent ↗A method and system are provided for determining an imminent failure of a non-volatile memory array. The method includes: performing a first array integrity read of the memory array until an error is detected; determining that the error is not error correction code (ECC) correctable, wherein a first word line voltage associated with the error is characterized as being a first threshold voltage; performing a second array integrity read of the memory array until all bits of the memory array indicate a predetermined state, wherein a second word line voltage associated with all of the bits indicating the predetermined state is a second threshold voltage; and comparing a difference between the first and second threshold voltages to a predetermined value.
1. A method for determining an imminent failure of a non-volatile memory array, the method comprising:
performing a first array integrity read of the non-volatile memory array until an error is detected;
determining that the error is not error correction code (ECC) correctable, wherein a first word line voltage associated with the error is characterized as being a first threshold voltage;
performing a second array integrity read of the memory array until all bits of the memory array indicate a predetermined state, wherein a second word line voltage associated with all of the bits being the predetermined state is a second threshold voltage, and wherein the predetermined state corresponds to an all erased state or an all programmed state; and
comparing a difference between the first and second threshold voltages to a predetermined value.
2. The method of claim 1 , wherein the first array integrity read indicates a read error.
3. The method of claim 1 , wherein the method is performed during a diagnostic mode of the non-volatile memory array.
4. The method of claim 1 , wherein the first array integrity read is accomplished by performing read operations of the memory array while sweeping a word line read voltage from an initial word line voltage to the first word line voltage.
5. The method of claim 1 , wherein performing the second array integrity read of the non-volatile memory array until all bits of the non-volatile memory array indicate a predetermined state further comprises checking a check sum value to determine when all bits of the non-volatile memory array indicate the predetermined state.
6. The method of claim 5 , wherein checking the check sum value further comprises the check sum value being a first value when all bits of the non-volatile memory array are programmed, and the check sum value being a second value when all bits of the memory array are erased, wherein the first value is not equal to the second value, wherein the first value and the second value are different from any other checksum value associated with the memory array.
7. The method of claim 1 , wherein comparing the difference between the first and second threshold voltages to the predetermined value further comprises indicating the imminent failure of the non-volatile memory array when the difference between the first and second threshold voltage is outside a predetermined range based on the predetermined value.
8. The method of claim 1 , wherein the second array integrity read is accomplished by performing read operations of the non-volatile memory array while sweeping a word line read voltage from the first word line voltage to the second word line voltage.
9. The method of claim 1 , wherein performing a second array integrity read of the non-volatile memory array until all bits of the non-volatile memory array indicate a predetermined state further comprises reading all array locations and comparing logic states of the read locations to the predetermined state.
10. A system comprising:
a memory array having a plurality of memory cells, each memory cell of the plurality of memory cells coupled to a word line and a bit line;
a threshold voltage modulator coupled to the word line, the threshold voltage modulator for providing a range of voltage levels to the word line during a diagnostic mode of the system;
an error correction code (ECC) decoder coupled to the memory array; and
a memory controller coupled to the memory array, the threshold voltage modulator, and the ECC decoder, the memory controller for controlling a first array integrity read operation of the memory array until a read error is detected, the memory controller for determining that the read error is not ECC correctable, wherein a first word line voltage associated with the read error is characterized as being a first threshold voltage, the memory controller for controlling a second array integrity read operation of the memory array until all bits of the memory array indicate a predetermined state, wherein a second word line voltage associated with all of the bits indicating the predetermined state is a second threshold voltage and the predetermined state corresponds to an all erased state or an all programmed state, and the memory controller for comparing a difference between the first and second threshold voltages to a predetermined value.
11. The system of claim 10 , wherein the memory controller is further characterized as being for indicating an imminent failure of the memory array when the difference between the first and second threshold voltage is greater than the predetermined value.
12. The system of claim 10 , wherein the memory array comprises a plurality of flash memory cells.
13. The system of claim 10 , further comprising an address sequencer coupled to the memory array, the address sequencer for selecting each of the plurality of memory cells during the first and second array integrity read operations.
14. The system of claim 10 , further comprising a check sum register coupled to the memory array, a check sum value stored in the check sum register is used to determine when all bits of the memory array indicate the predetermined state.