Patent Application

App. No. 12/790,999

Abstract

Claims (29)

1 . A method for fabricating a semiconductor chip grid array package, the method comprising:

providing an electrically conductive sheet having a chip facing surface on one side and an external facing surface on the other side;

etching channels in the chip facing surface of the electrically conductive sheet to define grid array pads in the form of a die attach pad and a plurality of connector pads, wherein the channels are etched to a depth of at least 60% of the thickness of the conductive sheet;

mounting a semiconductor die onto the die attach pad;

electrically connecting the connector pads to respective external connection terminals on the die;

encapsulating the die, channels and connector pads in an encapsulating material; and

etching the external facing surface of the electrically conductive sheet to electrically isolate the grid array pads from each other, wherein the etching the external facing surface is characterized by removing areas of the electrically conductive sheet interposed between adjacent grid array pads, and wherein the etching the external facing surface forms a stud protruding from each of the connector pads.

2 . The method for fabricating a semiconductor chip grid array package of claim 1 , wherein the die attach pad has an external mounting surface planar with mounting surfaces of each said stud protruding from each of the connector pads.

3 . The method for fabricating a semiconductor chip grid array package of claim 1 , wherein the channels are etched to a depth of at least 70% of the thickness of the conductive sheet.

4 . The method for fabricating a semiconductor chip grid array package of claim 3 , wherein the channels are etched to a depth of between 70% to 80% of the thickness of the conductive sheet.

5 . The method for fabricating a semiconductor chip grid array package of claim 1 , wherein the stud has a depth of no more than 40% of the thickness of the conductive sheet.

6 . The method for fabricating a semiconductor chip grid array package of claim 5 , wherein the stud has a depth of no more than 30% of the thickness of the conductive sheet.

7 . The method for fabricating a semiconductor chip grid array package of claim 6 , wherein the stud has a depth of between 20% to 30% of the thickness of the conductive sheet.

8 . The method for fabricating a semiconductor chip grid array package of claim 1 , wherein the electrically connecting is performed by wire bonding.

9 . The method for fabricating a semiconductor chip grid array package of claim 1 , wherein the stud has a maximum width that is at least 30% smaller than a maximum width of the connector pad from which it protrudes.

10 . The method for fabricating a semiconductor chip grid array package of claim 1 , wherein the stud protruding from each of the connector pads is a rod having a circular cross section.

11 . The method for fabricating a semiconductor chip grid array package of claim 10 , wherein the rod has a maximum diameter that is at least 30% smaller than a maximum width of the connector pad from which it protrudes.

12 . The method for fabricating a semiconductor chip grid array package of claim 1 , wherein the electrically conductive sheet is of sufficient size to allow for the fabricating of numerous semiconductor chip grid array packages, and the method includes a further step of singulating the semiconductor chip grid array package from other semiconductor chip grid array packages fabricated on the electrically conductive sheet.

13 . A semiconductor chip grid array package comprising:

a die attach pad and a plurality of connector pads;

a semiconductor die mounted on the die attach pad, the semiconductor die having external connection terminals electrically connected respectively to the connector pads;

an encapsulating material that encapsulates the die and connector pads;

a stud protruding from each of the connector pads for providing an external electrical contact for the semiconductor chip grid array package, wherein each of the connector pads and respective studs are formed from an electrically conductive sheet, and the connector pads are of a thickness of at least 60% of the thickness of the conductive sheet and the respective studs are of a thickness of no more than 40% of the thickness of the conductive sheet.

14 . The semiconductor chip grid array package of claim 13 , wherein the die attach pad has an external mounting surface planar with mounting surfaces of each stud protruding from each of the connector pads.

15 . The semiconductor chip grid array package of claim 13 , wherein the connector pads have a thickness of at least 70% of the thickness of the conductive sheet and the respective studs have a thickness of no more than 30% of the thickness of the conductive sheet.

16 . The semiconductor chip grid array package of claim 13 , wherein the connector pads have a thickness of between 70% to 80% of the thickness of the conductive sheet and the respective studs have a thickness of between 20% to 30% of the thickness of the conductive sheet.

17 . The semiconductor chip grid array package of claim 13 , wherein the stud protruding from each of the connector pads is a rod having a circular cross section.

18 . The semiconductor chip grid array package of claim 13 , wherein the stud has a maximum width that is at least 30% smaller than a maximum width of the connector pad from which it protrudes.

19 . The semiconductor chip grid array package of claim 17 , wherein the rod has a maximum diameter that is at least 30% smaller than a maximum width of the connector pad from which it protrudes.

Assignments (16)