Word line fault detection
View Patent ↗In a memory having a word line driver and a ROM having N bit positions and a plurality of rows in which each row is coupled to a corresponding word line of the word line driver and stores a unique N bit value, a method includes activating, by the word line driver, a selected word line, and, for each bit position, determining whether a value of a true bit line of the bit position is at a same logic state as a value of a complementary bit line of the bit position when the word line driver activates the selected word line. In response to determining that a value of the true bit line is at the same logic state as the value of the complementary bit line for any of the N bit positions, providing a multiple word line fault indicator indicating that multiple word lines are activated simultaneously.
1. A memory comprising:
an address decoder configured to receive an address and select a word line as a selected word line from a plurality of word lines;
a word line driver coupled to the address decoder and configured to activate the selected word line;
a read only memory (ROM) coupled to the word line driver and having N bit positions, wherein each row of the ROM is coupled to a corresponding word line from the word line driver and stores an unique N bit value, wherein N is an integer value greater than or equal to one; and
detection logic coupled to the ROM, wherein the detection logic is configured to:
for each bit position of the N bit positions, determine whether a value of a first bit line of the bit position is at a same logic state as a value of a second bit line of the bit position when the word line driver activates the selected word line, and
provide a first indicator indicative of a multiple word line fault based on whether the first bit line is at the same logic state as the second bit line for any of the N bit positions.
2. The memory of claim 1 , wherein the first bit line is further characterized as a true bit line, and the second bit line is further characterized as a complementary bit line.
3. The memory of claim 1 , further comprising a data array coupled to the word line driver, wherein each row of the data array is coupled to a corresponding word line from the word line driver.
4. The memory of claim 1 , wherein the ROM, for each bit position of each word line, comprises a transistor at an intersection of the word line and the first bit line if the bit position is programmed to a first logic state and comprises a transistor at an intersection of the word line and the second bit line if the bit position is programmed to a second logic state, different from the first logic state.
5. The memory of claim 1 , wherein the first indicator indicates whether or not multiple word lines of the memory are activated simultaneously when the selected word line is activated.
6. The memory of claim 5 , wherein the ROM further comprises a word line on bit line, and the detection logic is configured to use a logic state of the word line on bit line to provide a second indicator indicative of whether or not at least one of the plurality of word lines of the memory is activated when the word line driver activates the selected word line.
7. The memory of claim 6 , wherein, for each word line, the ROM further comprises a transistor at an intersection of the word line and the word line on bit line.
8. The memory of claim 6 , wherein the detection logic is configured to provide a word line fault indicator to indicate occurrence of a word line fault in the memory when the first indicator indicates multiple word lines of the memory are activated simultaneously or the second indicator indicates none of the plurality of word lines of the memory is activated.
9. The memory of claim 1 , further comprising:
word line fault profiling logic coupled to the detection logic and configured to determine a type of word line fault based on indications of a multiple word line fault provided by the first indicator and indications of whether or not at least one of the word lines of the memory is activated provided by the second indicator, wherein the type comprises one of a group consisting of a soft error rate fault or a transitional fault.
10. In a memory having a word line driver coupled to a data array and to a read only memory (ROM), the ROM having N bit positions and a plurality of rows in which each row is coupled to a corresponding word line from the word line driver and stores a unique N bit value, wherein N is an integer value greater than or equal to one, a method comprising:
activating, by the word line driver, a selected word line;
for each bit position of the N bit positions, determining whether a value of a true bit line of the bit position is at a same logic state as a value of a complementary bit line of the bit position when the word line driver activates the selected word line; and
in response to determining that a value of the true bit line is at the same logic state as the value of the complementary bit line for any of the N bit positions, providing a multiple word line fault indicator indicating that multiple word lines are activated simultaneously.
11. The method of claim 10 , wherein, for each bit position of the N bit positions, each of the bit line and the complementary bit line implements a dynamic OR operation.
12. The method of claim 10 , wherein the ROM further comprises a word line on bit line, the method further comprising:
using the word line on bit line to provide a word line on indicator indicative of whether or not at least one of the word lines of the memory is activated when the word line driver activates the selected word line.
13. The method of claim 12 , further comprising:
providing a word line fault indicator to indicate occurrence of a word line fault in the memory when the multiple word line fault indicator indicates that multiple word lines are activated simultaneously or the word line on indicator indicates that none of the word lines of the memory are activated.
14. The method of claim 12 , wherein the word line on bit line implements a dynamic OR operation.
15. The method of claim 12 , further comprising:
prior to the word line driver activating the selected word line, precharging the true bit line of each bit position, the complementary bit line of each bit position, and the word line on bit line to a predetermined voltage.
16. In a memory having a word line driver coupled to a data array and to a word line fault detection array, the word line fault detection array having N bit positions and a plurality of rows in which each row is coupled to a corresponding word line from the word line driver and stores a unique N bit value, wherein N is an integer value greater than or equal to one, a method comprising:
activating, by the word line driver, a selected word line;
for each bit position of the N bit positions:
performing a first logical OR operation on true bit values in the bit position of any activated word lines of the word line fault detection array to provide a first result;
performing a second logical OR operation on complementary bit values in the bit position of any activated word lines of the word line fault detection array to provide a second result; and
performing a logical AND operation using the first and second result of the particular bit position to obtain a third result; and
using the third result for each of the bit positions to provide a multiple word line fault indicator indicative of whether or not multiple word lines are activated simultaneously when the word line driver activates the selected word line.
17. The method of claim 16 , wherein the word line fault detection array is implemented as a read only memory (ROM).
18. The method of claim 16 , wherein the word line fault detection array further comprises a word line on bit line, the method further comprising:
using the word line on bit line to provide a word line on indicator indicative of whether or not at least one of the plurality of word lines of the memory is activated when the word line driver activates the selected word line.
19. The method of claim 18 , further comprising:
when multiple word lines of the memory are activated simultaneously or none of the word lines of the memory are activated, providing a word line fault indicator to indicate occurrence of a word line fault in the memory.
20. The method of claim 16 , wherein, for each bit position of the N bit positions, each of the bit line and the complementary bit line implements a dynamic OR operation.