Buffer apparatus, integrated circuit and method of reducing a portion of an oscillation of an output signal
View Patent ↗A buffer apparatus for a communications bus comprises a driver circuit having an output. An amplifier circuit having an input is coupled to the output of the driver circuit. The driver circuit is arranged to generate, when in use, a drive signal having a waveform that comprises a step therein so as to substantially suppress generation by the amplifier circuit of a portion of an oscillation of an output signal.
1. A buffer apparatus for a communications bus, the apparatus comprising:
a driver circuit having an output;
an amplifier circuit having an input coupled to the output of the driver circuit; and
a signal monitor coupled to the input of the amplifier circuit, wherein
the driver circuit is arranged to generate a drive signal having a waveform that comprises a step therein so as to substantially suppress generation by the amplifier circuit of a portion of an oscillation of an output signal,
the signal monitor monitors a differential input signal of the amplifier circuit in order to detect when the output signal reaches a predetermined intermediate level below a predetermined pulse output level, and
the signal monitor is arranged to trigger generation of the step when the output signal reaches the predetermined intermediate level.
2. The apparatus as claimed in claim 1 , wherein the waveform has a rising edge comprising the step.
3. The apparatus as claimed in claim 1 , wherein the signal monitor comprises:
a comparator, coupled to the input of the amplifier circuit, and arranged to trigger generation of the step in response to the differential input signal of the amplifier circuit being substantially zero value.
4. The apparatus as claimed in claim 1 , wherein the signal monitor is arranged to trigger generation of the step in response to the output signal reaching a predetermined signal margin preceding the predetermined intermediate level relative to a slew direction of the output signal.
5. The apparatus as claimed in claim 4 , wherein the predetermined signal margin is determined by an offset of the signal monitor.
6. The apparatus as claimed in claim 1 , wherein the portion of the oscillation of the output signal generated by the amplifier circuit has, in an absence of the step, an expected signal level, the step being located so as to reduce the expected signal level of the portion of the oscillation.
7. The apparatus as claimed in claim 1 , wherein the portion of the oscillation of the output signal is an overshoot or an undershoot.
8. The apparatus as claimed in claim 1 , wherein the step is located in the waveform so that the portion of the oscillation is less than a predetermined signal threshold corresponding to a logic level.
9. The apparatus as claimed in claim 1 , wherein the drive signal comprises a Sandcastle waveform.
10. The apparatus as claimed in claim 9 , wherein the Sandcastle waveform is a three level Sandcastle waveform.
11. The apparatus as claimed in claim 1 , wherein the driver circuit comprises:
a voltage converter, and
a controller coupled to the voltage converter, the controller being arranged to control the voltage converter in order to generate the waveform comprising the step.
12. The apparatus as claimed in claim 1 , further comprising:
an idle mode and a signal mode, wherein the waveform comprising the step is generated upon a transition from the idle mode to the signal mode.
13. A master module apparatus for a communications bus, the master module apparatus comprising the buffer apparatus as claimed in claim 1 .
14. The apparatus as claimed in claim 13 further comprising:
a signal detector arranged to generate a logic level in response to an input signal thereto being equal to or exceeding a predetermined signal threshold, wherein
the step is located in the waveform so that the portion of the oscillation is less than the predetermined signal threshold corresponding to the logic level.
15. The apparatus as claimed in claim 14 , wherein the signal detector does not generate the logic level in response to the portion of the oscillation of the output signal.
16. A distributed system interface master module apparatus comprising the buffer apparatus as claimed in claim 1 .
17. An integrated circuit for a communications bus, the integrated circuit comprising:
a driver circuit having an output;
an amplifier circuit having an input coupled to the output of the driver circuit; and
a signal monitor coupled to the input of the amplifier circuit; wherein
the driver circuit is arranged to generate a drive signal having a waveform that comprises a step therein so as to substantially suppress generation by the amplifier circuit of a portion of an oscillation of an output signal,
the signal monitor monitors a differential input signal of the amplifier circuit in order to detect when the output signal reaches a predetermined intermediate level below a predetermined pulse output level, and
the signal monitor is arranged to trigger generation of the step when the output signal reaches the predetermined intermediate level.
18. A method of reducing a portion of an oscillation of an output signal for a communications bus, the method comprising:
generating a drive signal having a waveform;
monitoring a differential input signal of an amplifier circuit in order to detect when the output signal reaches a predetermined intermediate level below a predetermined pulse output level;
triggering generation of a step in the waveform of the drive signal when the output signal reaches the predetermined intermediate level;
applying the drive signal to an input of the amplifier circuit, wherein
the amplifier circuit generates an output signal in response to the drive signal, generation of a portion of an oscillation component of the output signal being substantially suppressed by the presence of the step in the waveform.
19. The apparatus as claimed in claim 17 , wherein the signal monitor comprises:
a comparator, coupled to the input of the amplifier circuit, and arranged to trigger generation of the step in response to the differential input signal of the amplifier circuit being substantially zero value.
20. The apparatus as claimed in claim 17 , wherein the signal monitor is arranged to trigger generation of the step in response to the output signal reaching a predetermined signal margin preceding the predetermined intermediate level relative to a slew direction of the output signal.