IP Library Granted Patent US 7,378,298
Granted Patent B2
US 7,378,298 · App. 11/524,457 · Granted May 27, 2008

Method of making stacked die package

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Quick Facts
Patent No.
US 7,378,298
App. No.
11/524,457
Granted
May 27, 2008
Kind
B2
Abstract

A method of making a stacked die package ( 39 ) includes placing a first flip chip die ( 16 ) on a base carrier ( 12 ) and electrically connecting the first flip chip die ( 16 ) to the base carrier ( 12 ). A second flip chip die ( 18 ) is attached back-to-back to the first flip chip die ( 16 ) and electrically connected to the base carrier ( 12 ) with a plurality of insulated wires ( 20 ). A mold compound ( 36 ) is formed over the first and second dice and one surface of the base carrier.

Claims (29)

1. A method of making a stacked die package, comprising:

placing a first flip chip die on a base carrier;

electrically connecting the first flip chip die to the base carrier;

attaching a second flip chip die back-to-back to the first flip chip die; and

electrically connecting the second flip chip die to the base carrier with a plurality of insulated wires, wherein first ends of the insulated wires are bonded to respective bumps on respective die bonding pads of the second flip chip die and second ends of the insulated wires are bonded to the base carrier.

2. The method of making a stacked die package of claim 1 , wherein the die bonding pads of the second flip chip die are laid out in an area array.

3. The method of making a stacked die package of claim 1 , wherein the die bonding pads of the second flip chip die are situated along a periphery of the second flip chip die.

4. The method of making a stacked die package of claim 1 , wherein the first and second flip chip dice have substantially the same length and substantially the same width.

5. The method of making a stacked die package of claim 1 , wherein the second flip chip die is larger than the first flip chip die.

6. The method of making a stacked die package of claim 1 , wherein at least one of the insulated wires crosses over another of the insulated wires.

7. The method of making a stacked die package of claim 1 , further comprising performing a molding operation to encapsulate the first and second flip chip dice, the insulated wires and at least a portion of the base carrier.

8. The method of making a stacked die package of claim 7 , wherein the second flip chip die is attached to the first flip chip die with one of a tape and an epoxy.

9. The method of making a stacked die package of claim 8 , wherein the base carrier is one of a substrate and a lead frame.

10. The method of making a stacked die package of claim 9 , wherein the first flip chip die is electrically connected to the base carrier with a plurality of flip chip interconnections.

11. A method of making a stacked die package, comprising;

placing a first flip chip die on a base carrier;

electrically connecting the first flip chip die to the base carrier;

attaching a second flip chip die back-to-back to the first flip chip die, the second flip chip die having an area array of die bonding pads; and

electrically connecting the second flip chip die to the base carrier with a plurality of insulated wires.

12. The method of making a stacked die package of claim 11 , further comprising performing a molding operation to encapsulate the first and second flip chip dice, the insulated wires and at least a portion of the base carrier.

13. The method of making a stacked die package of claim 11 , wherein the first and second flip chip dice have substantially the same length and substantially the same width.

14. The method of making a stacked die package of claim 11 , wherein the second flip chip die is larger than the first flip chip die.

15. A method of making a plurality of stacked die packages, comprising:

placing a plurality of first flip chip dice on a base carrier;

electrically connecting the first flip chip dice to the base carrier;

attaching a plurality of second flip chip dice back-to-back to respective ones of the first flip chip dice, thereby forming a plurality of die stacks;

electrically connecting the second flip chip dice to the base carrier with a plurality of insulated wires, wherein the second flip chip dice have an area array of die bonding pads; and

performing a molding operation to encapsulate the first and second flip chip dice, the insulated wires and at least a portion of the base carrier.

16. The method of making a plurality of stacked die packages of claim 15 , further comprising performing a singulating operation to separate adjacent ones of the die stacks, thereby forming the plurality of stacked die packages.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
323.01(C) ASSIGNMENT OR CHANGE OF NAME IMPROPERLY FILED AND RECORDED BY ANOTHER PERSON AGAINST OWNER'S PATENT Recorded Oct 3, 2019
From: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 052459/0656 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2017
From: NORTH STAR INNOVATIONS INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 041717/0736 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037694/0264 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0719 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Sep 24, 2008
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 021570/0449 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2006
From: LO, WAI-YEW
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 018324/0911 →