Data processor coupled to a sequencer circuit that provides efficient scalable queuing and method
View Patent ↗A data processor includes a single-token-record memory, a sequence circuit, and a memory controller. The single-token-record memory has a plurality of first storage locations. The sequencer circuit is coupled to the single-token-record memory. The sequencer circuit, responsive to a request to place a token in a tail-end of a queue, either stores said token into one of the plurality of first storage locations if the single-token-record memory stores no greater than a predetermined number of tokens associated with the tail-end of the queue, or stores the token with at least one additional token and a pointer to a next storage location into one of a plurality of second storage locations otherwise. The memory controller is coupled to the sequencer circuit to store the token with the at least one additional token and the pointer in a location of a multi-token-record memory having the plurality of second storage locations.
1. A data processor comprising:
a single-token-record memory having a plurality of first storage locations;
a sequencer circuit coupled to said single token-record memory, wherein said sequencer circuit, responsive to a request to place a token in a tail-end of a queue, stores said token into one of said plurality of first storage locations if said single-token-record memory stores no greater than a predetermined number of tokens associated with said tail-end of said queue, and stores said token with at least one additional token and a pointer to a next storage location into one of a plurality of second storage locations if said single-token-record memory stores more than the predetermined number of tokens; and
a memory controller coupled to said sequencer circuit, the memory controller to provide a communication path through which the sequencer stores said token with said at least one additional token and said pointer in a location of a multi-token-record memory when said single-token-record memory stores more than the predetermined number of tokens, said multi-token-record memory having said plurality of second storage locations.
2. The data processor of claim 1 further comprising:
a plurality of processor cores coupled to said sequencer circuit and said memory controller; and
wherein said sequencer circuit provides a selected token to one of said plurality of processor cores to cause said one of said plurality of processor cores to process data associated with said selected token.
3. The data processor of claim 1 further comprising:
a network interface block coupled to said sequencer circuit, and said memory controller, and said network interface block having an input for receiving a packet from a network, and in response thereto, providing said packet to said memory controller for storage in a memory and providing said token to said sequencer circuit.
4. The data processor of claim 3 wherein said memory further includes said multi-token-record memory.
5. The data processor of claim 4 wherein said single-token-record memory, said sequencer circuit, said memory controller, and said network interface block are formed on a single integrated circuit, and wherein said memory is external to said single integrated circuit.
6. The data processor of claim 1 wherein a number of tokens included in said plurality of tokens is determined by a width of an optimal transaction of a bus between said memory controller and said multi-token-record memory.
7. The data processor of claim 1 wherein said predetermined number of tokens is one token.
8. The data processor of claim 1 wherein said at least one additional token is two additional tokens.
9. A data processor comprising:
a single-token-record memory having a plurality of first storage locations;
a sequencer circuit coupled to said single-token-record memory, wherein said sequencer circuit, responsive to a request to dequeue a token from a head-end of a queue, reads said token associated with said data packet from one of said plurality of first storage locations if said single-token-record memory stores more than a predetermined number of tokens associated with said head-end of said queue, and reads said token along with at least one additional token from one of a plurality of second storage locations and stores said additional tokens in said single-token-record memory, if said single-token-record memory stores less than the predetermined number of tokens; and
a memory controller coupled to said sequencer circuit, the memory controller to provide a communication path through which the sequencer reads said token and said at least one additional token from said plurality of second storage locations in a multi-token-record memory when said single-token-record memory stores less than the predetermined number of tokens.
10. The data processor of claim 9 further comprising:
a plurality of processor cores coupled to said sequencer circuit and said memory controller; and
wherein said sequencer circuit provides said token to one of said plurality of processor cores to cause said one of said plurality of processor cores to process data associated with said token.
11. The data processor of claim 9 further comprising:
a network interface block coupled to said sequencer circuit, and said memory controller, and said network interface block having an input for receiving a packet from a network, and in response thereto, providing said packet to said memory controller for storage in a memory and providing said token to said sequencer circuit.
12. The data processor of claim 11 wherein said memory further includes said multi-token-record memory.
13. The data processor of claim 12 wherein said single-token-record memory, said sequencer circuit, said memory controller, and said network interface block are formed on a single integrated circuit, and wherein said memory is external to said single integrated circuit.
14. The data processor of claim 11 wherein a number of tokens included in said token and said additional tokens is determined by a width of an optimal transaction of a bus between said memory controller and said multi-token memory.
15. The data processor of claim 9 wherein said predetermined number of tokens is zero tokens.
16. The data processor of claim 9 wherein said at least one additional token is two additional tokens.
17. A method for controlling queuing in a data processor, the method comprising:
receiving a token enqueue request;
transmitting a first token associated with said token enqueue request to a queuing mechanism;
determining a first number of tokens in a tail-end of a queue associated with said first token stored in a single-token-record memory;
if said first number is less than or equal to a first predetermined number, storing said first token in said single-token-record memory; and
if said first number is greater than said first predetermined number, storing said first token with at least one additional token and a pointer to a next storage location in a multi-token-record memory.
18. The method of claim 17 further comprising:
receiving a request to dequeue a second token from a head-end of said queue;
determining a second number of tokens in said head-end of said queue and associated with said second token stored in said single-token-record memory;
if said second number is greater than a second predetermined number, transmitting a selected token associated with the data to one of a plurality of processor cores; and
if said second number is equal to said second predetermined number, transmitting said selected token associated with the data to one of a plurality of processor cores from said multi-token-record memory, and transferring said at least one additional token from said multi-token-record memory to said single-token-record memory.
19. The method of claim 18 wherein said first predetermined number is one token and said second predetermined number is zero tokens.
20. The method of claim 17 wherein said at least one additional token is two additional tokens.