Read reference technique with current degradation protection
View Patent ↗A set of reference cells is used for sensing the data values stored at bit cells of a memory device. In response to an event, the reference cell providing the highest output of the set is selected as the reference cell to be used for subsequent memory access operations. The remaining reference cells are disabled so that they can recover back to or near their original non-degraded states. At each successive event, the set of reference cells can be reassessed to identify the reference cell that provides the highest output at that time and the memory device can be reconfigured to utilize the reference cell so identified. By utilizing the reference cell having the highest output to provide the read reference and disabling the remaining reference cells, the likelihood of the read reference falling below a minimum threshold can be reduced.
1. A method comprising:
determining, at a first time, a first reference cell of a plurality of reference cells associated with a plurality of bit cells of a bit cell array of a memory device as having the highest output current of the plurality of reference cells at the first time; and
sensing a data value stored at a first bit cell of the plurality of bit cells using a first output current of the first reference cell.
2. The method of claim 1 , further comprising:
determining, at a second time subsequent to the first time, a second reference cell of the plurality of reference cells as having the highest output current of the plurality of reference cells at the second time; and
sensing a data value stored at a second bit cell of the plurality of bit cells using a second output current of the second reference cell.
3. The method of claim 1 , further comprising:
disabling each reference cell of the plurality of reference cells except the first reference cell for a first duration between the first time and the second time; and
disabling each reference cell of the plurality of reference cells except the second reference cell for a second duration following the second time.
4. The method of claim 3 , wherein:
determining the first reference cell as having the highest output current of the plurality of reference cells at the first time comprises determining the first reference cell as having the highest output current of the plurality of reference cells in response to a first event; and
determining the second reference cell as having the highest output current of the plurality of reference cells at the second time comprises determining the second reference cell as having the highest output current of the plurality of reference cells in response to a second event subsequent to the first event.
5. The method of claim 4 , wherein the first event and the second event each respectively comprises one selected from a group consisting of: a power-on event; a reset event; an interrupt event; and a lapse of a predetermined duration.
6. The method of claim 3 , further comprising:
determining, at a third time subsequent to the second time, the first reference cell of the plurality of reference cells as having the highest output current of the plurality of reference cells at the third time; and
sensing a data value stored at a third bit cell of the plurality of bit cells using a third output current of the first reference cell.
7. The method of claim 6 , further comprising:
disabling each reference cell of the plurality of reference cells except the first reference cell for a first duration between the first time and the second time; and
disabling each reference cell of the plurality of reference cells except the second reference cell for a second duration between the second time and the third time; and
disabling each reference cell of the plurality of reference cells except the first reference cell for a third duration following the third time.
8. The method of claim 1 , further comprising:
disabling each reference cell of the plurality of reference cells except the first reference cell for a duration following the first time.
9. A method comprising:
providing a memory comprising a bit cell array, a plurality of reference cells associated with a plurality of bit cells of the bit cell array, and a sense amplifier;
at a first event, configuring the sense amplifier to utilize an output current of a first reference cell of the plurality of reference cells in response to determining the output current of the first reference cell is the highest output current of the plurality of reference cells at the first event;
at a second event subsequent to the first event, configuring the sense amplifier to utilize an output current of a second reference cell of the plurality of reference cells in response to determining the output current of the second reference cell is the highest output current of the plurality of reference cells at the second event.
10. The method of 9 , further comprising:
at a third event, configuring the sense amplifier to utilize the output current of the first reference cell in response to determining the output current of the first reference cell is the highest output current of the plurality of reference cells at the third event.
11. The method of claim 10 , wherein the third event is subsequent to the second event.
12. The method of claim 10 , wherein the third event is subsequent to the first event and prior to the second event.
13. The method of claim 9 , further comprising:
for a first duration following the first event, sensing data values stored at bit cells of the plurality of bit cells using the output current of the first reference cell; and
for a second duration following the second event, sensing data values stored at bit cells of the plurality of bit cells using the output current of the second reference cell.
14. The method of claim 9 , wherein:
configuring the sense amplifier to utilize the output current of the first reference cell comprises disabling the plurality of reference cells except the first reference cell; and
configuring the sense amplifier to utilize the output current of the second reference cell comprises disabling the plurality of reference bit-cells except the second reference cell.
15. A memory device comprising:
a bit cell array comprising a plurality of bit cells;
a plurality of reference cells associated with the plurality of bit cells;
a sense amplifier comprising an input to receive a reference current, the sense amplifier configured to sense data values stored at bit cells of the bit cell array based on the reference current; and
a reference controller configured to provide an output current of a first reference cell of the plurality of reference cells to the sense amplifier as the reference current for sensing a bit cell of the plurality of bit cells in response to determining the first reference cell as having the highest output current of the plurality of reference cells.
16. The memory device of claim 15 , wherein the reference controller is configured to determine the first reference cell in response to an event.
17. The memory device of claim 16 , wherein the event comprises one selected from a group consisting of: a power-on event; a reset event; an interrupt event; and a lapse of a predetermined duration.
18. The memory device of claim 15 , wherein the reference controller comprises:
a comparator comprising a first input coupled to a current electrode of a first reference cell of the plurality of reference cells, a second input coupled to a current electrode of a second reference cell of the plurality of reference cells, the comparator configured to provide an output value representative of a comparison of a first current detected at the first input and a second current detected at the second input; and
a word line driver comprising a first word line coupled to a control electrode of the first reference cell of the plurality of reference cells and a second word line coupled to a control electrode of the second reference cell, the word line driver configured to selectively enable one of the first word line and the second word line based on the output value of the comparator.
19. The memory device of claim 18 , wherein the reference controller further comprises:
a current summation module configured to provide the reference current based on a current of at least one of the first reference cell and the second reference cell.
20. The memory device of claim 15 , wherein the memory device comprises a non-volatile memory device.