IP Library Granted Patent US 7,583,216
Granted Patent B2
US 7,583,216 · App. 11/863,631 · Granted Sep 1, 2009

Adjustable DAC and applications thereof

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Quick Facts
Patent No.
US 7,583,216
App. No.
11/863,631
Granted
Sep 1, 2009
Kind
B2
Abstract

A digital to analog converter (DAC) includes at least one digital to analog conversion module and a gated termination. The at least one digital to analog conversion module is coupled to convert at least one bit of a digital signal into an analog signal. The gated termination is coupled to an analog output of the at least one digital to analog conversion module to provide a first termination when a termination selection signal is in a first state and to provide a second termination when the termination selection signal is in a second state.

Claims (61)

1. A digital to analog converter (DAC) comprises:

at least one digital to analog conversion module coupled to convert at least one bit of a digital signal into an analog signal, the digital to analog converter comprising:

a first current source coupled to a first supply voltage source;

a first switch; and

a second switch, wherein, when the at least one bit is in a first state, the first switch is enabled to steer current of the first current source to a dump node and, when the at least one bit is in a second state, the second switch is enable to steer the current of the first current source to an analog output;

a third switch operable to couple the dump node to a second supply voltage source when the at least one bit is in the first state, wherein voltage of the second supply voltage source is less than a voltage of the first supply voltage source and

a power regulator that produces the second supply voltage, wherein the power regulator responds accordingly to maintain regulation of the second supply voltage as the current from the dump node changes; and

a gated termination coupled to the analog output of the at least one digital to analog conversion module to provide a first termination when a termination selection signal is in a first state and to provide a second termination when the termination selection signal is in a second state.

2. The DAC of claim 1 , wherein the current source comprises:

a variable current source that provides a first current when the termination selection signal is in the first state and provides a second current when the termination selection signal is in the second state.

3. The DAC of claim 1 , wherein the gated termination comprises:

an impedance; and

a switch coupled in a series with the impedance, wherein, when the termination selection signal is in the first state, the switch is open to provide the first termination and, when the termination selection signal is in the second state, the switch is closed to provide the second termination.

4. The DAC of claim 1 further comprises:

an input for receiving the termination selection signal.

5. The DAC of claim 1 further comprises:

an operating conditions module coupled to:

determine at least one operating condition of the DAC; and

generate the termination selection signal based on the at least one operating condition.

6. The DAC of claim 1 , wherein the digital signal comprises video data.

7. The DAC of claim 1 , further comprising:

a bus coupled to the at least one digital to analog conversion module;

a random access memory coupled to the bus; and

a processing module coupled to the bus.

8. The DAC of claim 7 , further comprising:

an audio DAC module coupled to the bus.

9. A digital to analog converter (DAC) comprises:

a plurality of digital to analog conversion modules coupled to convert a digital signal into an analog signal, wherein a digital to analog conversion module of the plurality of digital to analog conversion modules includes:

a current source coupled to provide a first current when the DAC is in a first mode and to provide a second current when the DAC is in a second mode, wherein the second current is greater than the first current;

a first switch;

a second switch, wherein, when at least one bit of the digital signal is in a first state, the first switch is enabled to steer the first or second current to a dump node and, when the at least one bit is in a second state, the second switch is enable to steer the first or second current to an analog output; and

a power regulator that produces the second supply voltage, wherein the power regulator responds accordingly to maintain regulation of the second supply voltage as the current from the dump node changes.

10. The DAC of claim 9 , wherein the digital to analog conversion module further comprises:

a third switch operable to couple the dump node to a second supply voltage source when the at least one bit is in the first state, wherein voltage of the second supply voltage source is less than voltage of a first supply voltage source coupled to the current source.

11. The DAC of claim 10 further comprises:

a gated termination coupled to the analog output to provide a first termination when a termination selection signal is in a first state and to provide a second termination when the termination selection signal is in a second state.

12. The DAC of claim 11 , wherein the gated termination comprises:

an impedance; and

a switch coupled in a series with the impedance, wherein, when the termination selection signal is in the first state, the switch is open to provide the first termination and, when the termination selection signal is in the second state, the switch is closed to provide second termination.

13. The DAC of claim 12 further comprises:

an input for receiving the termination selection signal.

14. The DAC of claim 12 further comprises:

an operating conditions module coupled to:

determine at least one operating condition of the DAC; and

generate the termination selection signal based on the at least one operating condition.

15. A method, comprising:

in response to determining a first digital to analog conversion module is in a first mode, providing a first current from a current source;

in response to determining a first digital to analog conversion module is in a second mode, providing a second current from the current source, the second current greater than the first current;

receiving a digital signal at the first digital to analog conversion module;

in response to determining a first bit of the digital signal is in a first state, steering the first current or the second current to a dump node; and

in response to determining the first bit of the digital signal is in a second state, steering the first current or the second current to an analog output; and

regulating the second supply voltage to maintain a voltage as the current from the dump node changes.

16. The method of claim 15 , wherein the current source is coupled to a first supply voltage source, and farther comprising:

in response to determining the first bit of the digital signal is in the first state, coupling the dump node to a second supply voltage source.

17. The method of claim 16 , wherein a voltage of the second supply voltage source is less than voltage of the first supply voltage source.

18. The method of claim 15 , further comprising:

coupling the analog output to a first termination when a termination selection signal is in a first state and coupling the analog output to a second termination when the termination selection signal is in a second state.

19. The method of claim 18 , further comprising:

determining at an operating condition of the DAC; and

generating the termination selection signal based on the operating condition.

20. The method of claim 15 , wherein the digital signal comprises video data.

Assignments (15)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2017
From: NORTH STAR INNOVATIONS INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 041717/0736 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 037354 FRAME: 0773. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT RELEASE. Recorded Aug 15, 2016
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, LLC
Reel/Frame 039723/0777 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2016
From: SIGMATEL, LLC
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037583/0428 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037354/0734 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037354/0773 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0854 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037355/0838 →
CHANGE OF NAME Recorded Nov 23, 2015
From: SIGMATEL INC.
To: SIGMATEL, LLC
Reel/Frame 037152/0127 →
SECURITY AGREEMENT Recorded Nov 12, 2013
From: SIGMATEL, LLC
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031626/0218 →
SECURITY AGREEMENT Recorded Jun 17, 2013
From: SIGMATEL, LLC
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030628/0636 →
SECURITY AGREEMENT Recorded May 10, 2010
From: SIGMATEL, LLC
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 024358/0439 →
SECURITY AGREEMENT Recorded Mar 16, 2010
From: SIGMATEL, LLC
To: CITIBANK, N.A.
Reel/Frame 024079/0406 →
SECURITY AGREEMENT Recorded Feb 3, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 023882/0834 →
SECURITY AGREEMENT Recorded Jul 9, 2008
From: SIGMATEL, INC.
To: CITIBANK, N.A.
Reel/Frame 021212/0372 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 28, 2007
From: FELDER, MATTHEW D.; MAY, MARCUS W.; MAY, MICHAEL R.
To: SIGMATEL, INC.
Reel/Frame 019897/0494 →