Asymmetric spacers and asymmetric source/drain extension layers
View Patent ↗A method of forming a semiconductor device is provided in which a substrate ( 102 ) is provided which has a gate dielectric layer ( 106 ) disposed thereon, and a gate electrode ( 116 ) having first and second sidewalls is formed over the gate dielectric layer. First ( 146 ) and second ( 150 ) extension spacer structures are formed adjacent the first and second sidewalls, respectively. In the resulting device: (a) the first and second extension spacer structures have different dimensions; (b) the first and second extension spacer structures comprise first and second distinct materials; (c) the device has asymmetric source/drain extensions ( 162 ); and/or (d) the device has an oxide layer ( 160 ) disposed between the first extension spacer structure and the gate electrode, and either (i) the device has no dielectric layer disposed between the second extension spacer structure and the gate electrode, or (ii) the device has a second dielectric layer disposed between the second extension spacer structure and the gate electrode, and the first dielectric layer is substantially thicker than the second dielectric layer.
1. A semiconductor device, comprising:
a substrate having a gate dielectric layer disposed thereon;
a gate electrode disposed over the gate dielectric layer, said gate electrode having first and second sidewalls; and
first and second extension spacer structures disposed adjacent to said first and second sidewalls, respectively; and
source and drain regions and a layer of semiconductor material selected from the group consisting of SiGe and SiGeC, said layer being disposed between said first extension spacer structure and said source region, wherein the layer of semiconductor material is not disposed between the second extension spacer structure and the drain;
wherein the semiconductor device has at least one characteristic selected from the group consisting of: (a) the first and second extension spacer structures comprise first and second distinct materials; (b) the device has source/drain extensions that are asymmetrically disposed about the gate electrode; and (c) the device has a first dielectric layer disposed between the first extension spacer structure and the gate electrode, and either (i) the device has no dielectric layer disposed between the second extension spacer structure and the gate electrode, or (ii) the device has a second dielectric layer disposed between the second extension spacer structure and the gate electrode, and the first dielectric layer is substantially thicker than the second dielectric layer.
2. The device of claim 1 , wherein the device has a first dielectric layer disposed between the first extension spacer structure and the gate electrode, and the device has no dielectric layer disposed between the second extension spacer structure and the gate electrode.
3. The device of claim 1 , wherein the device has a first dielectric layer disposed between the first extension spacer structure and the gate electrode, wherein the device has a second dielectric layer disposed between the second extension spacer structure and the gate electrode, and wherein the first dielectric layer is substantially thicker than the second dielectric layer.
4. The device of claim 1 , wherein the first and second extension spacer structures comprise first and second distinct materials.
5. The device of claim 1 , wherein the device has source/drain extensions that are asymmetrically disposed about the gate electrode, and wherein the source/drain extensions comprise a material selected from the group consisting of SiGe and SiGeC.
6. The device of claim 1 , further comprising source/drain regions disposed in the substrate adjacent to the first and second extension spacer structures, and wherein the source/drain regions are aligned with the first and second extension spacer structures.
7. A method for forming a semiconductor device, comprising:
providing a substrate having a gate dielectric layer disposed thereon;
forming a gate electrode over the gate dielectric layer, the gate electrode having first and second sidewalls; and
forming first and second extension spacer structures adjacent to the first and second sidewalls, respectively; and
forming source and drain regions and a layer of semiconductor material selected from the group consisting of SiGe and SiGeC, said layer being disposed between said first extension spacer structure and said source region, wherein the layer of semiconductor material is not disposed between the second extension spacer structure and the drain;
wherein the semiconductor device has at least one characteristic selected from the group consisting of: (a) the first and second extension spacer structures comprise first and second distinct materials; (b) the device has source/drain extensions that are asymmetrically disposed about the gate electrode; and (c) the device has a first dielectric layer disposed between the first extension spacer structure and the gate electrode, and either (i) the device has no dielectric layer disposed between the second extension spacer structure and the gate electrode, or (ii) the device has a second dielectric layer disposed between the second extension spacer structure and the gate electrode, and the first dielectric layer is substantially thicker than the second dielectric layer.
8. The method of claim 7 , wherein the device has a first dielectric layer disposed between the first extension spacer structure and the gate electrode, and the device has no dielectric layer disposed between the second extension spacer structure and the gate electrode.
9. The method of claim 7 , wherein the device has a first dielectric layer disposed between the first extension spacer structure and the gate electrode, wherein the device has a second dielectric layer disposed between the second extension spacer structure and the gate electrode, and wherein the first dielectric layer is substantially thicker than the second dielectric layer.
10. The method of claim 7 , wherein the first and second extension spacer structures comprise first and second distinct materials.
11. The method of claim 7 , the device has source/drain extensions that are asymmetrically disposed about the gate electrode, and wherein the asymmetrically grown source/drain extensions comprise a material selected from the group consisting of SiGe and SiGeC.
12. The method of claim 7 , wherein the
source/drain regions are disposed in the substrate adjacent to the first and second extension spacer structures such that the source/drain regions are aligned with the first and second extension spacer structures.
13. The method of claim 7 , further comprising forming an extension implant region self-aligned to the gate electrode prior to forming the extension spacer structures.
14. The method of claim 7 , wherein the step of forming the extension spacer structures comprises the steps of:
depositing a dielectric film over the substrate and gate electrode; and
anisotropically etching the dielectric film.
15. The method of claim 7 , wherein the step of forming the first and second extension spacer structures comprises the steps of:
disposing a first dielectric film over the gate electrode;
selectively etching the first dielectric film to remove a portion thereof adjacent to the first side of the gate electrode, thus defining a first region in which the first dielectric film has been removed;
disposing a second dielectric film within the first region; and
etching the first and second dielectric films to define the first and second extension spacer structures.
16. The method of claim 7 , wherein the step of forming the first and second extension spacer structures comprises the steps of:
disposing a first dielectric film over the gate electrode;
disposing a mask over the first dielectric film, thereby defining a masked region and an unmasked region, the unmasked region including a portion of the first dielectric film adjacent to the first side of the gate electrode;
removing the first dielectric film from the unmasked region;
forming a second dielectric film within the unmasked region;
stripping the mask; and
etching the first and second dielectric films to define the first and second extension spacer structures.
17. The method of claim 7 , wherein the step of forming the first and second extension spacer structures comprises the steps of:
disposing a first dielectric film over the gate electrode;
removing a portion of the first dielectric film adjacent to the first side of the gate electrode while leaving a portion of the first dielectric film adjacent to the second side of the gate electrode;
disposing a second dielectric film adjacent to the first side of the gate electrode; and
etching the second dielectric film to define the second extension spacer structure.
18. The method of claim 17 , wherein the step of removing a portion of the first dielectric film adjacent to the first side of the gate electrode while leaving a portion of the first dielectric film adjacent to the second side of the gate electrode defines the first extension spacer structure.