FinFET structure with contacts
View Patent ↗A FinFET, which by its nature has both elevated source/drains and an elevated channel that are portions of an elevated semiconductor portion that has parallel fins and one source/drain on one side of the fins and another source/drain on the other side of the fins, has all of the source/drain contacts away from the fins as much as reasonably possible. The gate contacts extend upward from the top surface of the elevated semiconductor portion. The gate also extends upward from the top surface of the elevated semiconductor portion. The contacts are located between the fins where the gate is below the height of the elevated semiconductor portion so the contacts are as far as reasonably possible from the gate, thereby reducing gate to drain capacitance and providing additional assistance to alignment tolerance.
1. A semiconductor device comprising:
a semiconductor structure located over a dielectric, wherein the semiconductor structure includes:
a first current electrode portion running generally in a first horizontal direction;
a second current electrode portion running generally in the first horizontal direction;
a plurality of fin portions, each fin portion located between the first current electrode portion and the second current electrode portion, each fin portion having a first side wall and a second side wall;
a gate structure running generally in the first horizontal direction over the plurality of fin portions, wherein the gate structure has a first current electrode side sidewall and a second current electrode side sidewall;
wherein each fin portion of the plurality of fin portions includes a first location of a plurality of locations where the first current electrode side sidewall overlies the fin portion;
wherein the first current electrode portion includes a plurality of gate adjacent areas, wherein each gate adjacent area is defined as running in a second horizontal direction from a first location of the plurality of first locations, the second horizontal direction being orthogonal to the first horizontal direction;
a plurality of contacts electrically contacting the first current electrode portion, each contact of the plurality of contacts has a base, wherein the base of each contact of the plurality of contacts is located over an area of the first current electrode portion between the areas of two adjacent gate adjacent areas of the plurality of gate adjacent areas;
each fin portion of the plurality of fin portions includes a second location of a plurality of second locations where the second current electrode side sidewall overlies the fin portion;
the second current electrode portion includes a second plurality of gate adjacent areas, wherein each gate adjacent area of the second plurality of gate adjacent areas is defined as running in a second horizontal direction from a second location of the plurality of second locations; and
a second plurality of contacts electrically contacting the second current electrode portion, each contact of the second plurality of contacts has a base, wherein the base of each contact of the second plurality of contacts is located over an area of the second current electrode portion between two adjacent gate adjacent areas of the plurality of gate adjacent areas; and
the plurality of electrical contacts is horizontally staggered with the second plurality of electrical contacts.
2. The semiconductor device of claim 1 wherein all of the base of each contact of the plurality of contacts is located over an area of the first current electrode portion other than the areas of the plurality of gate adjacent areas.
3. The semiconductor device of claim 1 wherein the each of the plurality of fin portions runs generally in the second horizontal direction.
4. The semiconductor device of claim 1 wherein each contact of the plurality of contacts is located on and electrically connected to silicide material located on and electrically connected to the first current electrode structure.
5. The semiconductor device of claim 1 wherein:
each fin portion of the plurality of fin portions includes a channel region of a plurality of channel regions;
the movement of carriers of in each channel region of the plurality of channel regions during operation is generally horizontal in direction.
6. The semiconductor device of claim 1 wherein the base of each contact of the plurality of contacts is located over an area of the first current electrode portion that is centered between two adjacent gate adjacent areas of the plurality of gate adjacent areas.
7. A semiconductor device comprising:
a semiconductor structure located over a dielectric, wherein the semiconductor structure includes:
a first current electrode portion running generally in a first horizontal direction;
a second current electrode portion running generally in the first horizontal direction;
a plurality of fin portions, each fin portion located between the first current electrode portion and the second current electrode portion, each fin portion having a first side wall and a second side wall;
a gate structure running generally in the first horizontal direction over the plurality of fin portions, wherein the gate structure has a first current electrode side sidewall and a second current electrode side sidewall;
wherein each fin portion of the plurality of fin portions includes a first location of a plurality of locations where the first current electrode side sidewall overlies the fin portion;
wherein the first current electrode portion includes a plurality of gate adjacent areas, wherein each gate adjacent area is defined as running in a second horizontal direction from a first location of the plurality of first locations, the second horizontal direction being orthogonal to the first horizontal direction;
a plurality of contacts electrically contacting the first current electrode portion, each contact of the plurality of contacts has a base, wherein the base of each contact of the plurality of contacts is located over an area of the first current electrode portion between the areas of two adjacent gate adjacent areas of the plurality of gate adjacent areas; and
the plurality of fin portions each run in a third horizontal direction, wherein the third horizontal direction is non orthogonal to the first horizontal direction and non orthogonal to the second horizontal direction.
8. A semiconductor device comprising:
a semiconductor structure located over a dielectric, wherein the semiconductor structure includes:
a first current electrode portion running generally in a first horizontal direction;
a second current electrode portion running generally in the first horizontal direction;
a first fin portion located between the first current electrode portion and the second current electrode portion, the first fin portion includes a first side wall;
a second fin portion located between the first current electrode portion and the second current electrode portion, the second fin portion includes a second side wall, the second side wall facing the first side wall with no portion of the semiconductor structure located there between;
a gate structure running generally in the first horizontal direction over the first fin portion and the second fin portion, wherein the gate structure has a first current electrode side sidewall and a second current electrode side sidewall;
wherein the first fin portion includes a first location where the first current electrode side sidewall overlies the first fin portion;
wherein the second fin portion includes a second location where the first current electrode side sidewall overlies the fin portion;
wherein the first current electrode portion includes a first gate adjacent area defined as running in a second horizontal direction from the first location, the second horizontal direction being orthogonal to the first horizontal direction;
wherein the first current electrode portion includes a second gate adjacent area defined as running in the second horizontal direction from the second location;
a current electrode contact having a base in electrical contact with the first current electrode portion, wherein the base is located over an area of the first current electrode portion at a location between the first gate adjacent area and the second gate adjacent; and
a first gate structure including a first gate portion located over the first fin portion, a second gate portion located over the second fin portion, and a third gate portion located between the first side wall of the first fin portion and the second sidewall of the second fin portion, wherein a top of the first gate portion and a top of the second gate portion are vertically separated by a greater distance from the dielectric than a top portion of the third gate portion.
9. A semiconductor device of claim 8 further comprising:
a third fin portion located between the first current electrode portion and the second current electrode portion, the third fin portion includes a third side wall;
a fourth fin portion located between the first current electrode portion and the second current electrode portion, the fourth fin portion includes a fourth side wall, the fourth sidewall facing the third sidewall with no portion of the semiconductor structure located there between;
wherein the third fin portion includes a third location where the first current electrode side sidewall overlies the third fin portion;
wherein the fourth fin portion includes a fourth location where the first current electrode side sidewall overlies the fourth fin portion;
wherein the first current electrode portion includes a third gate adjacent area defined as running in a second horizontal direction from the third location;
wherein the first current electrode portion includes a fourth gate adjacent area defined as running in the second horizontal direction from the fourth location;
a second current electrode contact having a base in electrical contact with the first current electrode portion, wherein the base is located over an area of the first current electrode portion at a location between a third gate adjacent area and the fourth gate adjacent area.
10. A semiconductor device of claim 8 further comprising:
a third fin portion located between the first current electrode portion and the second current electrode portion, the third fin portion includes a third side wall;
a fourth fin portion located horizontally between the first current electrode portion and the second current electrode portion, the fourth fin portion includes a fourth side wall, the fourth sidewall facing the third side wall with no portion of the semiconductor structure located there between,
wherein the third fin portion includes a third location where the second current electrode side sidewall overlies the third fin portion;
wherein the fourth fin portion includes a fourth location where the second current electrode side sidewall overlies the fin portion;
wherein the second current electrode portion includes a third gate adjacent area defined as running in a second horizontal direction from the third location;
wherein the second current electrode portion includes a fourth gate adjacent area defined as running in the second horizontal direction from the fourth location;
a second current electrode contact having a base in electrical contact with the second current electrode portion, wherein the base is located over an area of the second current electrode portion at a location between a third second gate adjacent area and the fourth gate adjacent area.
11. The semiconductor device of claim 8 wherein:
the first fin portion includes a first channel;
the second fin portion includes a second channel;
the movement of carriers in the first channel and in the second channel during operation is generally horizontal in direction.