Dual metal gate electrode semiconductor fabrication process and structure thereof
View Patent ↗A semiconductor fabrication process includes patterning a first gate electrode layer overlying a gate dielectric. A second gate electrode layer is formed overlying the first gate electrode layer and the gate dielectric. Portions of the second gate electrode layer overlying the first gate electrode layer are removed until the first and second gate electrode layers have the same thickness. A third gate electrode layer may be formed overlying the first and second gate electrode layers. The first gate electrode layer may comprise TiN and reside primarily overlying PMOS regions while the second gate electrode layer may comprise TaC or TaSiN and primarily overlie NMOS regions. Removing portions of the second gate electrode layer may include performing a chemical mechanical process (CMP) without masking the second gate electrode layer or forming a resist mask and etching exposed portions of the second gate electrode layer.
1. A method of forming gate electrodes in a semiconductor fabrication process, comprising:
forming a gate dielectric overlying a semiconductor substrate;
depositing a first gate electrode layer overlying the gate dielectric;
removing portions of the first gate electrode layer thereby exposing portions of the gate dielectric;
depositing a second gate electrode layer overlying the first gate electrode layer and exposed portions of the gate dielectric; and
removing the second gate electrode layer where it overlies the first gate electrode layer wherein remaining portions of the first and second gate electrode layers have substantially the same thickness, wherein a majority of the first gate electrode layer overlies a first well region of the substrate and wherein a majority of the second gate electrode layer overlies a second well region of the substrate, and wherein the first well region is an NWELL region and the first gate electrode layer is TiN and wherein the second well region is an PWELL region and the second gate electrode layer comprises TaSiN, TaC, or Ta x C y N z .
2. The method of claim 1 , further comprising depositing a third gate electrode layer overlying the first and second gate electrode layers.
3. The method of claim 1 , wherein the gate dielectric is selected from the group consisting of SiO 2 , Si 3 N 4 , and SiON.
4. The method of claim 1 , wherein removing the second gate electrode layer comprises performing a chemical mechanical polish (CMP) process without masking the second gate electrode layer.
5. The method in claim 1 , further comprising, prior to said removing of portions of the first gate electrode layer, patterning a hard mask overlying portions of the first gate electrode layer.
6. A semiconductor fabrication process, comprising:
depositing a first gate electrode layer overlying a gate dielectric;
patterning the first gate electrode layer;
depositing a second gate electrode layer overlying the patterned first gate electrode layer and the gate dielectric;
removing the second gate electrode layer where it overlies the patterned first gate electrode wherein a thickness of remaining portions of the second gate electrode layer is substantially equal to a thickness of the patterned first gate electrode layer, wherein a majority of the first gate electrode layer overlies a first well region of the substrate and wherein a majority of the second gate electrode layer overlies a second well region of the substrate, and wherein the first well region is an NWELL region and the first gate electrode layer is TiN and wherein the second well region is an PWELL region and the second gate electrode layer comprises TaSiN, TaC, or Ta x C y N z ;
depositing polycrystalline silicon (polysilicon) overlying the first and second gate electrode layers; and
selectively etching portions of the polysilicon and the underlying first and second gate electrode layers to form first and second gate electrodes.
7. The method of claim 6 , wherein removing the second gate electrode comprises performing a (chemical mechanical polish) process following depositing the second gate electrode layer.