Granted Patent B2

US 7,341,915 · App. 11/142,057 · Granted Mar 11, 2008

Abstract

Claims (53)

1. A method for forming a semiconductor device from a substrate comprising a bottom gate layer, a channel layer overlying the bottom gate layer, and a top gate structure formed over the channel layer, the method comprising:

depositing a hardmask comprising a first material interposed between a second material and a third material over a portion of the top gate structure;

encapsulating the hardmask and the top gate structure with an insulating material to form a spacer, said encapsulating comprising placing insulating material over the top gate structure, incorporating the insulating material with the first material of the hardmask, and depositing a passivating layer on an exposed portion of the top gate structure before placing the insulating material over the top gate structure;

forming a channel structure from the channel layer, the channel structure disposed under the spacer;

forming a bottom gate structure from the bottom gate layer, the bottom gate structure disposed under the channel structure; and

forming a source/drain contact around the bottom gate structure.

2. The method of claim 1 , wherein the step of depositing a hardmask comprises:

covering a portion of the top gate structure with the second material, the second material comprising oxide;

depositing the first material over the second material, the first material comprising nitride; and

placing the third material over the first material, the third material comprising oxide.

3. The method of claim 1 , wherein the step of depositing a passivating layer comprises oxidizing the top gate structure.

4. The method of claim 1 , wherein the substrate further comprises a top gate dielectric layer disposed over the channel layer and under the top gate structure, a portion of the insulating material is deposited over the top gate dielectric layer, and the step of encapsulating further comprises selectively removing the insulating material from the top gate dielectric layer to form the spacer.

5. The method of claim 1 , wherein the substrate further comprises a top gate dielectric layer disposed over the channel layer and under the top gate structure, a portion of the insulating material is deposited over the top gate dielectric layer, and the step of forming a channel structure comprises depositing a dielectric material over the top gate dielectric layer and spacer.

6. The method of claim 5 , wherein the dielectric material merges with the top gate dielectric layer and the step of forming a channel structure further comprises removing a portion of the dielectric material overlying the channel layer and surrounding the spacer.

7. The method of claim 5 , wherein a portion of the channel layer is removed to form the channel structure.

8. The method of claim 1 , wherein the step of forming a bottom gate structure comprises forming the bottom gate structure substantially vertically in alignment with the top gate structure.

9. The method of claim 1 , wherein the step of forming a bottom gate structure comprises depositing a second insulating material over at least a portion of the bottom gate layer, the spacer, and the channel structure.

10. The method of claim 9 , wherein the step of forming a bottom gate structure further comprises:

selectively removing a first portion of the second insulating material to expose a portion of the bottom gate layer while maintaining the spacer and channel structure encapsulated; and

removing a second portion of the second insulating material to expose a portion of the spacer.

11. The method of claim 10 , wherein the step of forming a bottom gate structure further comprises etching the bottom gate layer to form the bottom gate structure.

12. The method of claim 11 , wherein the step of etching the bottom gate layer comprises anisotropically and isotropically etching the bottom layer.

13. The method of claim 1 , wherein the step of forming a source/drain contact comprises:

placing a third insulating material over the spacer and around the bottom gate structure, after the step of forming a bottom gate structure;

forming a cavity in the third insulating material; and

transforming the cavity into a source/drain cavity.

14. The method of claim 13 , wherein the step of forming a source/drain contact further comprises depositing semiconductor material in the source/drain cavity.

15. The method of claim 14 , further comprising depositing a dielectric over the top gate structure and the semiconductor material.

16. A method of forming a semiconductor device from a substrate comprising a polygate stack including an insulator layer, a bottom gate layer overlying the insulator layer, a bottom gate dielectric layer overlying the bottom gate layer, a channel layer overlying the bottom gate dielectric layer, a top gate dielectric layer overlying the channel layer, and a top gate layer overlying the top gate dielectric layer, the method comprising:

covering the top gate layer with a first material comprising oxide;

depositing a second material comprising nitride over the first material;

placing a third material comprising oxide over the second material;

removing portions of the first material, second material, and third material to form a hardmask;

removing a portion of the top gate layer to form a top gate structure;

encapsulating the top gate structure and contacting the second material of the hardmask with an insulating material to form a spacer, said encapsulating comprising placing insulating material over the top gate structure and depositing a passivating layer on an exposed portion of the top gate structure before placing the insulating material over the top gate structure;

forming a channel structure from the channel layer, the channel structure disposed under the spacer and having a width that is greater than a width of the top gate structure;

forming a bottom gate structure from the bottom gate layer that is substantially vertically in alignment with the top gate structure; and

depositing semiconductor material around the bottom gate structure and in contact with the channel structure.

17. The method of claim 16 , further comprising

removing the spacer to expose the top gate structure; and

implanting a source/drain into the semiconductor material.

18. A method of forming a semiconductor device from a substrate comprising a polygate stack including an insulator layer, a bottom gate layer overlying the insulator layer, a bottom gate dielectric layer overlying the bottom gate layer, a channel layer overlying the bottom gate dielectric layer, a top gate dielectric layer overlying the channel layer, and a top gate layer overlying the top gate dielectric layer, the method comprising:

forming a hardmask over the top gate layer by:

covering the top gate layer with a first material comprising oxide;

depositing a second material comprising nitride over the first material; and

placing a third material comprising oxide over the second material;

removing portions of the first material, second material, and third material;

removing a portion of the top gate layer to form a top gate structure;

encapsulating the top gate structure and contacting the second material with an insulating material to form a spacer, said encapsulating comprising placing insulating material over the top gate structure and depositing a passivating layer on an exposed portion of the top gate structure before placing the insulating material over the top gate structure;

forming a channel structure from the channel layer, the channel structure disposed under the spacer and having a width that is greater than a width of the top gate structure;

forming a bottom gate structure from the bottom gate layer that is substantially vertically in alignment with the top gate structure;

depositing semiconductor material around the bottom gate structure and in contact with the channel structure; and

forming a source/drain from the deposited semiconductor material.

Assignments (23)