Multi-channel transistor structure and method of making thereof
View Patent ↗A method of forming an electronic device includes, forming a first channel coupled to a first current electrode and a second current electrode and forming a second channel coupled to the first current electrode and the second current electrode. The method also includes the second channel being substantially parallel to the first channel within a first plane, wherein the first plane is parallel to a major surface of a substrate over which the first channel lies. A gate electrode is formed surrounding the first channel and the second channel in a second plane, wherein the second plane is perpendicular to the major surface of the substrate. The resulting semiconductor device has a plurality of locations with a plurality of channels at each location. At small dimensions the channels form quantum wires connecting the source and drain.
1. An electronic device comprising:
a first current electrode;
a second current electrode;
a first channel coupled to the first current electrode and the second current electrode, and surrounded by a gate electrode in a first plane, wherein the first plane is perpendicular to a major surface of a substrate over which the first channel lies; and
a second channel coupled to the first current electrode and the second current electrode, and surrounded by the gate electrode in the first plane, wherein the second channel is substantially parallel to the first channel within a second plane, wherein the second plane is parallel to the major surface.
2. The electronic device of claim 1 , wherein the device further comprises a third channel coupled to the first current electrode and the second current electrode and surrounded by the gate electrode in the first plane, wherein the third channel is substantially parallel to the first channel within a third plane, wherein the third plane is perpendicular to the major surface.
3. The electronic device of claim 2 , wherein a composition of the first channel and a composition of the third channel each comprise a semiconductor.
4. The electronic device of claim 3 , wherein the composition of the first channel and a composition of the third channel are the same.
5. The electronic device of claim 3 , wherein the composition of the first channel and a composition of the third channel are different.
6. The electronic device of claim 2 , wherein the device further comprises a fourth channel coupled to the first current electrode and the second current electrode and surrounded by the gate electrode in the first plane, wherein the fourth channel is substantially parallel to the third channel within a fourth plane, wherein the fourth plane is parallel to the major surface.
7. The electronic device of claim 6 , wherein a composition of the third channel and a composition of the fourth channel each comprise a semiconductor.
8. The electronic device of claim 7 , wherein the composition of the first channel and a composition of the third channel are the same.
9. The electronic device of claim 8 , wherein a composition of the first channel and a composition comprises a semiconductor.
10. The electronic device of claim 9 , wherein the composition of the first channel and a composition of the third channel are the same.
11. The electronic device of claim 9 , wherein the composition of the first channel and a composition of the third channel are different.
12. The electronic device of claim 1 , wherein a composition of the first channel and a composition of the second channel each comprise a semiconductor.
13. The electronic device of claim 12 , wherein the composition of the first channel and a composition of the third channel are the same.
14. The electronic device of claim 1 , wherein a diameter of the first channel in the first plane is less than approximately 30 nanometers.
15. The electronic device of claim 14 , wherein a diameter of the first channel in the first plane is less than approximately 15 nanometers.
16. The electronic device of claim 15 , wherein a diameter of the first channel in the first plane is less than approximately 5.0 nanometers.
17. The electronic device of claim 1 further comprising a first dielectric region disposed between the first channel and the gate electrode, the first dielectric region surrounding the first channel in the first plane.
18. The electronic device of claim 17 further comprising a second dielectric region disposed between the second channel and the gate electrode, the second dielectric region surrounding the first channel in the first plane.
19. The electronic device of claim 17 , wherein a diameter of the first channel in the first plane is less than approximately 30 nanometers.
20. The electronic device of claim 19 , wherein a diameter of the second channel in the first plane is less than approximately 30 nanometers.