Mechanical integrity evaluation of low-k devices with bump shear
View Patent ↗A bump shear test is disclosed for evaluating the mechanical integrity of low-k interconnect stacks in an integrated circuit which includes a die test structure ( 11 ) having a stiff structural component ( 501, 502 ) positioned above and affixed to a conductive metal pad ( 103 ) formed in a last metal layer ( 104 ). The die test structure ( 11 ) may also include a dedicated support structure ( 41 ) below the conductive metal pad which includes a predetermined pattern of metal lines formed in the interconnect layers ( 18, 22, 26 ). After mounting the integrated circuit in a test device, a shear knife ( 601 ) is positioned for lateral movement to cause the shear knife to contact the stiff structural component ( 501 ). Any damage to the die test structure caused by the lateral movement of the shear knife may be assessed to evaluate the mechanical integrity of the interconnect stack.
1. A bump shear testing method for evaluating a semiconductor structure for mechanical integrity, comprising:
providing a semiconductor structure, said semiconductor structure comprising a die test structure having a stiff structural component positioned above and affixed to a conductive metal pad formed in a last metal layer and a dedicated test support structure underlying the conductive metal pad;
moving the shear knife laterally in relation to the semiconductor structure to cause the shear knife to contact the stiff structural component during lateral movement of the shear knife; and
assessing any damage to the die test structure caused by the lateral movement of the shear knife to evaluate the mechanical integrity of one or more interconnect layers in the dedicated test support structure of the semiconductor structure.
2. The bump shear testing method of claim 1 , where the die test structure having a stiff structural component comprises a copper stud in a solder ball.
3. The bump shear testing method of claim 1 , where the die test structure having a stiff structural component comprises a stud formed with a high modulus material selected from the group comprising copper, tantalum, tungsten or chromium.
4. The bump shear testing method of claim 1 , where the die test structure having a stiff structural component comprises a solder ball formed with a high modulus lead-free solder material.
5. The bump shear testing method of claim 1 , where the dedicated test support structure comprises a predetermined pattern of metal lines formed in one or more interconnect layers in the semiconductor structure.
6. The bump shear testing method of claim 5 , where the dedicated test support structure further comprises a plurality of low-k dielectric layers.
7. The bump shear testing method of claim 5 , where the predetermined pattern of metal lines comprises a parallel-type pattern of metal lines.
8. The bump shear testing method of claim 5 , where the predetermined pattern of metal lines comprises an orthogonal-type pattern of metal lines.
9. The bump shear testing method of claim 5 , where the predetermined pattern of metal lines comprises a random-type pattern of metal lines.
10. The bump shear testing method of claim 1 , where the semiconductor structure comprises a guard structure disposed in the interconnect layers and outside of a force region to protect the semiconductor structure from any fractures in the die test structure.
11. A method of testing a mechanical integrity measure of a low-k interconnect stack, the method comprising:
fabricating a semiconductor structure with a test structure comprising:
a stiff structural component affixed over a conductive metal pad formed in an upper layer of a low-k interconnect stack, and
a dedicated support structure below the conductive metal pad comprising a predetermined pattern of metal lines formed in the low-k interconnect stack;
performing a bump shear test on the test structure by aiming a shear knife at the stiff structural component; and
assessing a mechanical integrity measure for the low-k interconnect stack by determining whether the low-k interconnect stack passes the bump shear test.
12. The method of claim 11 , where the stiff structural component comprises a solder bump and an internal stud structure.
13. The method of claim 11 , where the stiff structural component comprises a stud structure.
14. The method of claim 13 , where the stud structure is formed of a stiff material selected from the group comprising copper, tantalum, tungsten or chromium.
15. The method of claim 11 , where the stiff structural component comprises a solder bump formed of a high modulus lead-free solder material.
16. The method of claim 11 , where the predetermined pattern of metal lines is affixed to the conductive metal pad.
17. The method of claim 16 , where the predetermined layout pattern of metallization and dielectric comprises a parallel-type pattern of metal lines, a perpendicular-type pattern of metal lines or a random-type pattern of metal lines.