Method of fabricating a MOS device with non-SiO
View Patent ↗A polycrystalline silicon layer is deposited on a gate dielectric and then a portion thereof is re-oxidized so as to form a thin layer of oxide between the poly-Si layer and the underlying gate dielectric. Subsequently, the poly-Si layer is converted to a fully-silicided form so as to produce a FUSI gate. The gate dielectric can be a high-k material, for example a Hf-containing material, or SION, or another non-SiO 2 dielectric. The barrier oxide layer is preferably less than 1 nm thick.
1. A method of fabricating a MOS device, comprising:
forming a layer of non-SiO 2 gate dielectric material on a substrate; and
forming a layer of polycrystalline silicon on said non-SiO 2 gate dielectric layer;
forming a layer of oxide between said polycrystalline silicon layer and said non-SiO 2 gate dielectric layer after said layer of polycrystalline silicon has been formed on said layer of non-SiO 2 gate dielectric material; and
converting said polycrystalline silicon to a fully-silicided form.
2. The MOS device fabrication method of claim 1 , wherein said oxide-layer has a thickness of less than 1 nm.
3. The MOS device fabrication method of claim 1 , wherein said non-SiO 2 gate dielectric material is a high-k dielectric material.
4. The MOS device fabrication method of claim 3 , wherein said non-SiO 2 gate dielectric material is a Hf-containing material.
5. The MOS device fabrication method of claim 1 , wherein said non-SiO 2 gate dielectric material is SiON.
6. A method of claim 1 , further comprising forming a non-SiO 2 gate dielectric and a FUSI gate electrode, with said layer of oxide situated between the gate electrode and the non-SiO 2 gate dielectric.
7. The method according to claim 6 , wherein the oxide layer between the gate electrode and the gate dielectric is less than 1 nm thick.
8. A method according to claim 6 , wherein the gate dielectric comprises a layer of high-k dielectric material.
9. A method according to claim 6 , wherein the gate dielectric comprises a layer of SiON.
10. The method according to claim 2 , wherein said gate dielectric material is a high-k dielectric material.
11. The method according to claim 2 , wherein said gate dielectric material is SiON.
12. The method according to claim 4 , further comprising forming a non-SiO 2 gate dielectric and a FUSI gate electrode, with said layer of oxide between the FUSI gate electrode and the non-SiO 2 gate dielectric.
13. The method according to claim 7 , wherein the non-SiO 2 gate dielectric comprises a layer of high-k dielectric material.
14. The method according to claim 1 , wherein said forming said layer of oxide includes lateral oxidation.
15. The method according to claim 1 , wherein said forming said layer of oxide includes oxidizing said polycrystalline silicon.
16. The method according to claim 3 , wherein said forming said layer of oxide includes oxidizing said polycrystalline silicon.
17. The method according to claim 4 , wherein said forming said layer of oxide includes oxidizing said polycrystalline silicon.
18. The method according to claim 5 , wherein said forming said layer of oxide includes oxidizing said polycrystalline silicon.
19. The method according to claim 6 , wherein said forming said layer of oxide includes oxidizing said polycrystalline silicon.
20. The method according to claim 2 , wherein said forming said layer of oxide includes oxidizing said polycrystalline silicon.