IP Library Granted Patent US 8,592,926
Granted Patent B2
US 8,592,926 · App. 13/273,389 · Granted Nov 26, 2013

Substrate bonding with metal germanium silicon material

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Quick Facts
Patent No.
US 8,592,926
App. No.
13/273,389
Granted
Nov 26, 2013
Kind
B2
Abstract

In one embodiment, a semiconductor structure including a first substrate, a semiconductor device on the first substrate, a second substrate, and a conductive bond between the first substrate and the second substrate that surrounds the semiconductor device to seal the semiconductor device between the first substrate and the second substrate. The conductive bond comprises metal, silicon, and germanium. A percentage by atomic weight of silicon in the conductive bond is greater than 5%.

Claims (49)

1. A semiconductor structure, comprising:

a first substrate;

a semiconductor device on the first substrate, a second substrate;

a conductive bond between the first substrate and the second substrate that surrounds the semiconductor device to seal the semiconductor device between the first substrate and the second substrate, wherein:

the conductive bond comprises metal, silicon, and germanium;

a multilayer stack located between the first substrate and the second substrate and formed on one of the first substrate or the second substrate, the multilayer stack includes a first layer comprising silicon, a second layer comprising polycrystalline silicon germanium, and a third layer comprising polycrystalline germanium, wherein the first layer is located closest to the one of the first substrate or the second substrate, the third layer is located furthest from the one of the first substrate or the second substrate, and the second layer is located between the first layer and the third layer;

wherein the conductive bond includes material formed from material of the first layer, material of the second layer, and material the third layer.

2. The structure of claim 1 , wherein the metal includes aluminum.

3. The structure of claim 2 , wherein the conductive bond includes a material that is characterized a ternary system including aluminum, silicon, and germanium.

4. The structure of claim 1 , wherein the conductive bond is characterized as a eutectic compound including aluminum, germanium, and silicon.

5. The structure of claim 1 wherein the second substrate includes a cavity located on an inner side of the second substrate facing the first substrate within the seal, the cavity overlying the semiconductor device, wherein a portion of the multilayer stack is located in the cavity.

6. The structure of claim 1 , wherein the semiconductor device is further characterized by the semiconductor device being a micro electromechanical system (MEMS) device.

7. The structure of claim 1 where the first substrate includes a bond pad electrically coupled to a structure of the semiconductor device, the bond pad is located outside the seal of the conductive bond.

8. The structure of claim 1 where the seal is characterized as a hermetic seal.

9. The structure of claim 1 wherein the first layer includes polycrystalline silicon.

10. The structure of claim 1 wherein the multilayer stack is formed on the second substrate.

11. The structure of claim 10 wherein the second substrate is part of a cap for the semiconductor device.

12. The structure of claim 1 wherein the first layer has a thickness in a range of 750-2500 Angstroms, the second layer has a thickness in a range of 500-2000 Angstroms, and the third layer has a thickness in a range of 2000-4000 Angstroms.

13. The structure of claim 1 wherein a germanium content of the second layer is in a range of 20-40 atomic percent.

14. A semiconductor structure, comprising:

a first substrate;

a micro electromechanical system (MEMS) device on the first substrate,

a second substrate;

a conductive bond between the first substrate and the second substrate that surrounds the MEMS device to hermetically seal the MEMS device between the first substrate and the second substrate, wherein:

the conductive bond is characterized as a eutectic compound that includes aluminum, germanium, and silicon;

a multilayer stack located between the first substrate and the second substrate and formed on one of the first substrate or the second substrate, the multilayer stack includes a first layer comprising silicon, a second layer comprising silicon germanium, and a third layer comprising germanium, wherein the first layer is located closest to the one of the first substrate or the second substrate, the third layer is located furthest from the one of the first substrate or the second substrate, and the second layer is located between the first layer and the third layer;

wherein the multilayer stack extends to the conductive bond.

15. The structure of claim 14 where the first substrate includes a bond pad electrically coupled to a structure of the MEMS device, the bond pad is located outside the hermetic seal of the conductive bond.

16. The structure of claim 14 wherein the second substrate includes a cavity located on an inner side of the second substrate facing the first substrate within the seal, the cavity overlying the MEMS device, wherein a portion of the multilayer stack is located in the cavity.

17. The structure of claim 14 wherein the first layer includes polycrystalline silicon, the second layer includes polycrystalline silicon germanium, and the third layer includes polycrystalline germanium.

18. The structure of claim 14 wherein the multilayer stack is formed on the second substrate.

19. A semiconductor structure, comprising:

a first substrate;

a micro electromechanical system (MEMS) device on the first substrate,

a second substrate;

a conductive bond between the first substrate and the second substrate that surrounds the MEMS device to hermetically seal the MEMS device between the first substrate and the second substrate, wherein:

the conductive bond is characterized as a eutectic compound that includes aluminum, germanium, and silicon;

a multilayer stack located between the first substrate and the second substrate and formed on one of the first substrate or the second substrate, the multilayer stack includes a first layer comprising silicon, a second layer comprising silicon germanium, and a third layer comprising germanium, wherein the first layer is located closest to the one of the first substrate or the second substrate, the third layer is located furthest from the one of the first substrate or the second substrate, and the second layer is located between the first layer and the third layer;

wherein the conductive bond includes material formed from material of the first layer, material of the second layer, and material the third layer.

20. The structure of claim 19 wherein the multilayer stack extends to the conductive bond.

21. A semiconductor structure, comprising:

a first substrate;

a semiconductor device on the first substrate,

a second substrate;

a conductive bond between the first substrate and the second substrate that surrounds the semiconductor device to seal the semiconductor device between the first substrate and the second substrate, wherein:

the conductive bond comprises metal, silicon, and germanium;

a multilayer stack located between the first substrate and the second substrate and formed on one of the first substrate or the second substrate, the multilayer stack includes a first layer comprising silicon, a second layer comprising polycrystalline silicon germanium, and a third layer comprising polycrystalline germanium, wherein the first layer is located closest to the one of the first substrate or the second substrate, the third layer is located furthest from the one of the first substrate or the second substrate, and the second layer is located between the first layer and the third layer;

wherein the multilayer stack extends to the conductive bond.

22. The structure of claim 21 wherein the conductive bond includes material formed from material of the first layer, material of the second layer, and material the third layer.

Assignments (30)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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323.01(C) ASSIGNMENT OR CHANGE OF NAME IMPROPERLY FILED AND RECORDED BY ANOTHER PERSON AGAINST OWNER'S PATENT Recorded Oct 3, 2019
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RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2017
From: NORTH STAR INNOVATIONS INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
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PATENT RELEASE Recorded Aug 17, 2016
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
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