Scheme of level shifter cell
View Patent ↗A system having voltage level shifting capabilities, the system includes a logic circuit and a multiple level voltage supply circuit; wherein the logic circuit comprises at least one PMOS transistor and at least one NMOS transistor; wherein the logic circuit receives an input signal, receives a voltage supply signal from the multiple level voltage supply circuit, and outputs an output signal via a first node; wherein the input signal has a low voltage swing between a low level supply voltage and a rail voltage; wherein the output signal has a high voltage swing between a high level supply voltage and the rail voltage; and wherein the multiple level voltage supply circuit selects, in response to a level of the output signal, whether to provide to the supply node of the logic circuit a high level supply voltage or a low level supply voltage.
1. A system having voltage level shifting capabilities, the system comprises a logic circuit and a multiple level voltage supply circuit;
wherein the logic circuit comprises at least one PMOS transistor and at least one NMOS transistor;
wherein the logic circuit receives an input signal, receives a voltage supply signal from the multiple level voltage supply circuit, and outputs an output signal via a first node;
wherein the input signal has a low voltage swing between a low level supply voltage and a rail voltage;
wherein the output signal has a high voltage swing between a high level supply voltage and the rail voltage;
wherein the multiple level voltage supply circuit selects, in response to a level of the output signal, whether to provide to the supply node of the logic circuit a high level supply voltage or a low level supply voltage.
2. The system according to claim 1 wherein the multiple level voltage supply circuit provides the high level supply voltage if the level of the output signal is high and provides the low level supply voltage if the level of the output signal is low.
3. The system according to claim 1 wherein the multiple level voltage supply circuit comprises a first inverter, a second inverter, a first PMOS transistor and a second PMOS transistor;
wherein the first inverter receives the output signal and inverts the output signal to provide a first inverted signal, the first inverted signal is provided to a gate of the first PMOS transistor and to the second inverter;
wherein the second inverter inverts the first inverted signal to provide a non inverted signal, the non inverted signal is provided to a gate of the second PMOS transistor;
wherein the source of the first PMOS inverter receives the high level supply voltage, the source of the second PMOS inverter receives the low level supply voltage and drains of the first and second PMOS transistors are connected to a second node.
4. The system according to claim 3 wherein the second inverter comprises an NMOS transistor that is more dominant than a PMOS transistor of the second inverter.
5. The system according to claim 3 wherein the first inverter is characterized by a low switching point.
6. A method for voltage level shifting capabilities, the method comprises:
receiving, by a logic circuit that comprises a PMOS transistor and an NMOS transistor, an input signal; wherein the input signal has a low voltage swing between a low level supply voltage and a rail voltage;
selecting, by a multiple level voltage supply circuit and in response to a level of an output signal of the logic circuit, whether to provide to the PMOS transistor a high level supply voltage or a low level supply voltage; and
outputting, by the logic circuit, an output signal that has a high voltage swing between a high level supply voltage and the rail voltage.
7. The method according to claim 6 wherein the selecting is followed by providing, by the multiple level voltage supply circuit, the high level supply voltage if the level of the output signal is high and providing, by the multiple level voltage supply circuit, the low level supply voltage if the level of the output signal is low.
8. The method according to claim 6 wherein the multiple level voltage supply circuit comprises an input node, a first inverter, a second inverter, a first PMOS transistor and a second PMOS transistor;
wherein drains of the first and second PMOS transistors are coupled to the PMOS transistor;
wherein the selecting is preceded by receiving the output signal by an input node of the multiple level voltage supply circuit;
wherein the selecting comprises:
inverting, by a first inverter, the output signal to provide a first inverted signal and providing the first inverted signal to a gate of the first PMOS transistor and to the second inverter;
inverting, by the first inverter, the first inverted signal to provide a non inverted signal and providing the non inverted signal to a gate of the second PMOS transistor; and
wherein the method comprises receiving, by the source of the first PMOS inverter, the high level supply voltage, and receiving, by the source of the second PMOS inverter the low level supply voltage.
9. The method according to claim 8 wherein the second inverter comprises an NMOS transistor that is more dominant than a PMOS transistor of the second inverter.
10. The method according to claim 8 wherein the first inverter is characterized by a low switching point.