IP Library Granted Patent US 8,018,018
Granted Patent B2
US 8,018,018 · App. 11/995,465 · Granted Sep 13, 2011

Temperature sensing device

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Quick Facts
Patent No.
US 8,018,018
App. No.
11/995,465
Granted
Sep 13, 2011
Kind
B2
Abstract

The present invention relates to an integrated device, comprising a semiconductor device formed on a semiconductor substrate, a temperature sensing element formed within a semi-conductive layer formed on the semiconductor substrate, an electrically insulating layer formed over the semi-conductive layer, a metal layer formed over the insulation layer and forming an electrical contact of the semiconductor device, and a thermal contact extending from the metal layer through the electrically insulating layer to a first region of the semi-conductive layer, wherein the first region of the semi-conductive layer is electrically isolated from the temperature sensing element. The present invention also relates to a method of forming a temperature sensing element for integration with a semiconductor device.

Claims (37)

1. An integrated device, comprising:

a semiconductor device formed on a semiconductor substrate;

a temperature sensing element formed within a semi-conductive layer formed on the semiconductor substrate;

an electrically insulating layer formed over the semi-conductive layer; and

a metal layer formed over the insulation layer and forming an electrical contact of the semiconductor device;

a thermal contact extending from the metal layer substantially through the electrically insulating layer adjacent to a first region of the semi-conductive layer, wherein the first region of the semi-conductive layer is electrically isolated from the temperature sensing element.

2. The device of claim 1 , further comprising between the first region and the temperature sensing element any one of:

a resistive region; and

at least one reversed P/N junction.

3. The device of claim 2 , wherein the at least one reversed P/N junctions forms any one of:

a diode;

a zener diode; and

a thyristor.

4. The device of claim 1 , wherein the metal layer substantially covers the semiconductor device and the temperature sensing element.

5. The device of claim 1 , wherein the temperature sensing element is formed on an outside edge of a die containing the semiconductor device.

6. The device of claim 1 , wherein the metal layer is at least 4 microns thick.

7. The device of claim 1 , wherein the thermal contact comprises a portion of the metal layer extending through an opening in the electrically insulating layer.

8. The device of claim 1 , further comprising a plurality of thermal contacts extending from the metal layer through the electrically insulating layer to a plurality of regions of the semi-conductive layer, wherein each of the plurality of regions is electrically isolated from the temperature sensing element.

9. The device of claim 8 , wherein the plurality of thermal contacts surround the temperature sensing element.

10. A method of forming a temperature sensing element for integration with a semiconductor device, comprising the steps of:

providing a semiconductor substrate;

forming a semiconductor device on said semiconductor substrate;

forming a temperature sensing element within a semi-conductive layer on said semiconductor substrate;

forming an electrically insulating layer over said semi-conductive layer; and

forming a metal layer over the electrically insulating layer, wherein the metal layer forms an electrical contact of the semiconductor device;

forming a thermal contact extending from the metal layer through the electrically insulating layer to a first region of the semi-conductive layer, wherein the first region of the semi-conductive layer is remote from the temperature sensing element and electrically isolated from the temperature sensing element.

11. The method of claim 10 , wherein the step of forming the thermal contact further comprises the step of:

forming an opening in the electrically insulating layer extending to the semi-conductive layer; and

depositing metal over the electrically insulating layer such that the metal layer extends through the opening to the semi-conductive layer.

12. The method of claim 10 , further comprising the step of forming between the first region and the temperature sensing element, any one of:

a resistive region; and

at least one reversed P/N junction.

13. The method of claim 10 , wherein the step of forming the metal layer further comprising forming the metal layer such that the metal layer substantially covers the semiconductor device and the temperature sensing element.

14. The method of claim 10 , wherein the step of forming the temperature sensing element further comprises locating the temperature sensing element on an outside edge of a die containing the semiconductor device.

15. The method of claim 10 , wherein the metal layer is at least 4 microns thick.

16. The method of claim 10 , further comprising the step of forming a plurality of thermal contacts extending from the metal layer through the electrically insulating layer to a plurality of regions of the semi-conductive layer, wherein each of the plurality of regions electrically isolated from the temperature sensing element.

17. The method of claim 16 , further comprising the step of locating the plurality of thermal contacts such that they surround the temperature sensing element.

Assignments (19)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0688 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2010
From: REYNES, JEAN-MICHEL; MARTY, ERIC; DERAM, ALAIN; SAUVEPLANE, JEAN-BAPTISTE
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 023849/0373 →