High performance CMOS radio frequency receiver
View Patent ↗A high performance radio frequency receiver includes a low noise amplifier with large binary and stepped gain control range, controlled impedance, and enhanced blocker immunity, for amplifying and converting a radio frequency signal to a current; a pulse generator for generating in-phase and quadrature pulses; a crossover correction circuit and pulse shaper for controlling a crossover threshold of the pulses and interaction between in-phase and quadrature mixers; and a double balanced mixer for combining the RF signal with the pulses to generate an intermediate frequency or baseband zero intermediate frequency current-mode signal. The in-phase and quadrature pulses have a duty cycle of 20-35%. The intermediate frequency signal and second order harmonics may be filtered with a high frequency low pass filter and a current injected complex direct-coupled filter. Decreased die size, current drain, cost, and complexity, as well as improvements in gain, 1/f noise, noise figure, sensitivity, and linearity may result.
1. A radio frequency receiver, comprising:
a low noise transconductance amplifier operable to amplify and convert a received voltage of a radio frequency signal to a first current;
a pulse generator operable to generate pulses from a periodic signal, the pulses having a duty cycle of 35% or less;
a crossover correction circuit to reduce overlap of the pulses;
a double balanced mixer operable to combine the first current with the pulses to produce a second current, the second current comprising an intermediate frequency signal; and
a direct coupled complex filter operable to filter the second current to a filtered analog signal;
where the crossover correction circuit is operable to control a crossover threshold of the pulses and where:
the pulses comprise in-phase pulses and quadrature pulses;
the crossover threshold comprises a crossing point of an amplitude of the in-phase pulses and the quadrature pulses, the crossing point selected to reduce the amount of time the in-phase pulses and quadrature pulses are simultaneously active; and
the intermediate frequency signal comprises an in-phase signal and a quadrature signal.
2. The radio frequency receiver of claim 1 , where the double balanced mixer comprises CMOS transistors and the crossover correction circuit is operable to bias a gate voltage of the CMOS transistors to select the crossing point.
3. The radio frequency receiver of claim 1 , where the duty cycle is between 20% and 35%.
4. The radio frequency receiver of claim 1 , where:
the pulses comprise in-phase pulses and quadrature pulses;
the in-phase pulses comprise a first pulse zero degrees out of phase from the periodic signal and a second pulse one hundred eighty degrees out of phase from the periodic signal; and
the quadrature pulses comprise a third pulse ninety degrees out of phase from the periodic signal and a fourth pulse two hundred seventy degrees out of phase from the periodic signal.
5. The radio frequency receiver of claim 1 , further comprising an active bias generation circuit configured to bias the amplifier such that low frequency bias noise in the radio frequency signal is inhibited in the presence of large blocking signals.
6. The radio frequency receiver of claim 5 , where the active bias generation circuit comprises a reference current source coupled to a supply voltage and a node; a first NMOS transistor with a source coupled to ground, a drain coupled to the node, and a gate coupled to the received voltage; and a second NMOS transistor with a source coupled to the received voltage, a drain coupled to the supply voltage, and a gate coupled to the node.
7. The radio frequency receiver of claim 1 , where the low noise transconductance amplifier is further operable to amplify and convert the received voltage of the radio frequency signal to the first current using step weighting and binary weighting.
8. The radio frequency receiver of claim 1 , further comprising a gain matching circuit operable to step up an impedance of the received voltage to match an input impedance of the low noise transconductance amplifier.
9. A radio frequency receiver, comprising:
a low noise transconductance amplifier operable to amplify and convert a received voltage of a radio frequency signal to a first current;
a pulse generator operable to generate pulses from a periodic signal, the pulses having a duty cycle of 35% or less;
a double balanced mixer operable to combine the first current with the pulses to produce a second current, the second current comprising an intermediate frequency signal; and
a direct coupled complex filter operable to filter the second current to a filtered analog signal,
where the pulses comprise in-phase pulses and quadrature pulses, and the pulse generator comprises a first latch operable to generate the quadrature pulses and a first latch output based on the periodic signal and a second latch output, and a second latch operable to generate the in-phase pulses and the second latch output based on the periodic signal and the first latch output.
10. The radio frequency receiver of claim 9 , where the first latch and the second latch comprise a gated clock circuit.
11. A method of receiving a radio frequency signal, comprising:
converting and amplifying a voltage of the radio frequency signal to a first current;
generating pulses from a periodic signal, the pulses having a duty cycle of 35% or less;
reducing overlap of the pulses;
mixing the first current with the pulses to produce a second current, the second current comprising an intermediate frequency signal; and
filtering the second current to a filtered analog signal;
where reducing the overlap of the pulses comprises correcting a crossover threshold of the pulses, and where:
the pulses comprise in-phase pulses and quadrature pulses;
correcting the crossover threshold comprises selecting a crossing point of the in-phase pulses and the quadrature pulses to reduce the amount of time the in-phase pulses and quadrature pulses are simultaneously active; and
the intermediate frequency signal comprises an in-phase signal and a quadrature signal.
12. The method of claim 11 , where correcting the crossover threshold comprises biasing a gate voltage of a CMOS transistor to select the crossing point.
13. The method of claim 11 , where the duty cycle is between 20% and 35%.
14. The method of claim 11 , where:
the pulses comprise in-phase pulses and quadrature pulses;
the in-phase pulses comprise a first pulse zero degrees out of phase from the periodic signal and a second pulse one hundred eighty degrees out of phase from the periodic signal; and
the quadrature pulses comprise a third pulse ninety degrees out of phase from the periodic signal and a fourth pulse two hundred seventy degrees out of phase from the periodic signal.
15. The method of claim 11 , further comprising step weighting and binary weighting the amplification of the voltage of the radio frequency signal to the first current.
16. The method of claim 11 , further comprising inhibiting low frequency bias noise in the radio frequency signal in the presence of large blocking signals.
17. A method of receiving a radio frequency signal, comprising:
converting and amplifying a voltage of the radio frequency signal to a first current;
generating pulses from a periodic signal, the pulses having a duty cycle of 35% or less;
mixing the first current with the pulses to produce a second current, the second current comprising an intermediate frequency signal; and
filtering the second current to a filtered analog signal,
where the pulses comprise in-phase pulses and quadrature pulses, and generating pulses comprises generating the quadrature pulses and a first latch output based on the periodic signal and a second latch output, and generating the in-phase pulses and the second latch output based on the periodic signal and the first latch output.
18. An analog front end of a radio frequency receiver, comprising:
a low noise amplifier operable to amplify and convert a received voltage of a radio frequency signal to a first current, the low noise amplifier configured to step weight and binary weight the amplification;
a pulse generator operable to generate in-phase and quadrature pulses based on a periodic signal, the in-phase and quadrature pulses having an approximately 25% duty cycle and comprising a first pulse zero degrees out of phase from the periodic signal, a second pulse one hundred eighty degrees out of phase from the periodic signal, a third pulse ninety degrees out of phase from the periodic signal, and a fourth pulse two hundred seventy degrees out of phase from the periodic signal;
a crossover correction circuit to reduce overlap of the in-phase and quadrature pulses; and
a mixer operable to combine the first current with the in-phase and quadrature pulses to produce a second current, the second current comprising an intermediate frequency signal;
where:
the crossover correction circuit is operable to control an amplitude crossover threshold of the in-phase and quadrature pulses, such that the in-phase and quadrature pulses are not active simultaneously; and
the analog front end further comprises a direct coupled complex filter operable to filter the intermediate frequency signal to a filtered analog signal.
19. A radio frequency receiver, comprising:
a low noise transconductance amplifier operable to amplify and convert a received voltage of a radio frequency signal to a first current;
a pulse generator operable to generate pulses from a periodic signal, the pulses having a duty cycle of 35% or less;
a crossover correction circuit to reduce overlap of the pulses;
a double balanced mixer operable to combine the first current with the pulses to produce a second current, the second current comprising an intermediate frequency signal; and
a direct coupled complex filter operable to filter the second current to a filtered analog signal;
an active bias generation circuit configured to bias the amplifier such that low frequency bias noise in the radio frequency signal is inhibited in the presence of large blocking signals;
where the active bias generation circuit comprises a reference current source coupled to a supply voltage and a node; a first NMOS transistor with a source coupled to ground, a drain coupled to the node, and a gate coupled to the received voltage; and a second NMOS transistor with a source coupled to the received voltage, a drain coupled to the supply voltage, and a gate coupled to the node.