Method of programming a memory having electrically programmable fuses
View Patent ↗An array of memory cells is arranged in a plurality of columns and rows, each of the memory cells including a programmable fuse connected to a predetermined bit line and in series with a select transistor. The select transistor has a first current electrode connected to a reference voltage terminal, a control electrode connected to a predetermined word line, and a second current electrode connected to the programmable fuse. The select transistor further has a semiconductor body adjacent to which the first current electrode and the second current electrode are located. These electrodes are separated by a channel. A signal terminal that is connected to the semiconductor body receives an input signal to forward bias the channel to the first current electrode during programming of the programmable fuse to increase a programming current of the programmable fuse.
1. A method comprising:
providing an array of memory cells arranged in a plurality of columns and rows, each of the memory cells comprising a programmable fuse connected to a predetermined bit line and in series with a select transistor, the select transistor comprising a first current electrode connected to a reference voltage terminal, a control electrode connected to a predetermined word line and a second current electrode connected to the programmable fuse, the select transistor further comprising a semiconductor body in which the first current electrode and the second current electrode are located and separated by a channel;
selecting a memory cell to identify a selected memory cell from the array of memory cells for programming; and
in response to the selecting, providing a current to the semiconductor body of the select transistor of the selected memory cell to forward bias the channel to the first current electrode during programming of the programmable fuse of the selected memory cell to increase a programming current through select transistor and programmable fuse of the selected memory cell to result in programming of the selected memory cell.
2. The method of claim 1 further comprising:
coupling row circuitry and column circuitry to the array of memory cells, the column circuitry providing a programming voltage to each of a plurality of bit lines and selecting a predetermined column in which an accessed memory cell is connected to, the row circuitry selecting a single row of cells which in combination with the selected predetermined column determines the selected memory cell, the accessed memory cell forming a path to create the programming current; and
providing program control circuitry for providing the input signal to the semiconductor body of each select transistor only during a program operation of the array of memory cells.
3. The method of claim 2 further comprising:
implementing the select transistor in each of the memory cells as an N-channel metal oxide semiconductor transistor comprising a source as the first current electrode, a gate as the control electrode and a drain as the second current electrode; and
using a base of a parasitic bipolar transistor formed by the semiconductor body and the source and drain as the signal terminal to receive the input signal.
4. The method of claim 3 further comprising:
providing a switchable input current as the input signal.
5. The method of claim 3 further comprising:
providing a switchable input voltage as the input signal, the switchable input voltage having a value that increases the programming current and enables a reduction in physical size of the select transistor from a first size to a second size.
6. The method of claim 3 further comprising:
providing a switchable input voltage as the input signal, the switchable input voltage having a value that increases the programming current and enables a reduction in magnitude of programming voltage from a first value to a second value to further prevent accidental programming of memory cells connected to the selected predetermined column and unselected rows.
7. A method comprising:
providing an electrically programmable fuse having one of two possible impedance states in response to a programming current, the electrically programmable fuse having a first terminal for receiving a programming voltage and having a second terminal;
providing a select transistor having a first current electrode connected to the second terminal of the electrically programmable fuse, a control electrode for receiving a select signal, a second current electrode connected to a reference voltage terminal, and a body terminal connected to a transistor body in which the first current electrode and the second current electrode are positioned and separated by a channel, the body terminal provided to receive a switchable bias signal to forward bias the channel to the second current electrode to increase a programming current of the electrically programmable fuse;
applying a first set of signals to the select transistor when the electrically programmable fuse is selected for being programmed and a second set of signals to the select transistor when the electrically programmable fuse is deselected for being programmed;
asserting the switchable bias signal during a time that the first set of signals are being applied to the select transistor; and
de-asserting the switchable bias signal when the second set of signals are applied to the select transistor.
8. The method of claim 7 further comprising:
implementing the select transistor as an N-channel metal oxide semiconductor transistor comprising a drain as the first current electrode, a gate as the control electrode, and a source as the second current electrode; and
using a base of a parasitic bipolar transistor formed by the transistor body and the source and drain as the body terminal.
9. The method of claim 7 further comprising:
providing a switchable input voltage as the switchable bias signal, the switchable input voltage having a value that increases the programming current and enables a reduction in magnitude of programming voltage from a first value to a second value to further prevent accidental programming of memory cells connected to the selected predetermined column and unselected rows.
10. The method of claim 7 further comprising:
providing an array of memory cells in rows and columns, each memory cell in the array of memory cells comprising an electrically programmable fuse and a select transistor that are connected as recited in claim 7 ;
coupling row circuitry and column circuitry to the array of memory cells, the column circuitry providing a programming voltage to at least one of a plurality of bit lines thereby selecting a corresponding column to which accessed memory cells may be connected, the row circuitry selecting a row of cells which in combination with the selected corresponding column determines the accessed memory cell, the accessed memory cell forming a path to create the programming current; and
providing program control circuitry for providing the switchable bias signal to the transistor body of the select transistor only during a program operation of the array of memory cells.
11. The method of claim 10 further comprising:
providing a switchable input voltage as the switchable bias signal, the switchable input voltage having a value that increases the programming current and enables a reduction in magnitude of programming voltage from a first value to a second value to further prevent accidental programming of memory cells connected to the selected predetermined column and unselected rows.
12. The method of claim 7 further comprising:
providing a switchable input current as the switchable bias signal.
13. The method of claim 7 further comprising:
providing a switchable input voltage as the switchable bias signal, the switchable input voltage having a value that increases the programming current and enables a reduction in physical size of the select transistor from a first size to a second size.
14. A method comprising:
providing an electrically programmable fuse having a first terminal connected to a select line for receiving a select signal, and having a second terminal; and
coupling an N-channel metal oxide semiconductor (MOS) transistor to the second terminal of the electrically programmable fuse, the N-channel metal oxide semiconductor transistor having a drain, a gate, a source connected to a reference voltage terminal, the N-channel metal oxide semiconductor having a parasitic bipolar transistor comprising an emitter formed by the source, a collector formed by the drain, and a base formed by a transistor body of the N-channel metal oxide semiconductor transistor for receiving a switching body bias signal to selectively increase programming current conducted by the electrically programmable fuse when the electrically programmable fuse is being programmed;
applying a first set of signals to the N-channel MOS transistor when the electrically programmable fuse is selected for being programmed and a second set of signals to the N-channel MOS transistor when the electrically programmable fuse is deselected for being programmed;
asserting the switching body bias signal during a time that the first set of signals are being applied to the N-channel MOS transistor; and
de-asserting the switchable bias signal when the second set of signals are applied to the select transistor.
15. The method of claim 14 further comprising:
forming an array of columns and rows of electrically programmable cells, each electrically programmable cell comprising an electrically programmable fuse and an N-channel metal oxide semiconductor transistor as recited in claim 14 , wherein selectively increasing programming current in a selected electrically programmable cell reduces accidental programming of electrically programmable cells connected to a selected predetermined column and unselected rows.
16. The method of claim 14 further comprising:
using a voltage of substantially 0.7 volt as the switching body bias signal to increase the programming current conducted by the electrically programmable fuse when in a program mode of operation.