Metric for selective branch target buffer (BTB) allocation
View Patent ↗A method and data processing system allocates entries in a branch target buffer (BTB). Instructions are fetched from a plurality of instructions and one of the plurality of instructions is determined to be a branch instruction. A corresponding branch target address is determined. A determination is made whether the branch target address is stored in a branch target buffer (BTB). When the branch target address is not stored in the branch target buffer, an entry in the branch target buffer is identified for allocation to receive the branch target address based upon stored metrics such as data processing cycle saving information and branch prediction state. In one form the stored metrics are stored in predetermined fields of the entries of the BTB.
1. A method for branch target buffer (BTB) allocation in a pipelined data processing system, comprising:
fetching an instruction from a plurality of instructions and determining that the instruction is a branch instruction;
determining a branch target address corresponding to the branch instruction;
determining whether the branch target address is stored in a branch target buffer (BTB), wherein when the branch target address is not stored in the branch target buffer, identifying an entry in the branch target buffer for allocation to receive the branch target address;
determining whether to allocate the branch instruction based upon data processing cycle saving information; and
storing the data processing cycle saving information in the pipelined data processing system.
2. The method of claim 1 further comprising:
storing the data processing cycle saving information in a field of an entry of the BTB.
3. The method of claim 1 further comprising:
determining the data processing cycle saving information by determining a number of data processing cycles to be saved by using a presently stored branch target address in the entry.
4. The method of claim 1 further comprising:
determining the data processing cycle saving information by determining a difference between a savings in data processing cycles obtained by a presently stored target address in the entry and a savings in data processing cycles that would be realized in response to a subsequent access of the branch target address if the branch target address were stored in the BTB.
5. The method of claim 1 further comprising:
determining the data processing cycle saving information as an estimated number of data processing cycles that are saved on a subsequent access of the branch target address if the branch target address is stored in the entry in the branch target buffer.
6. The method of claim 1 further comprising:
determining whether to allocate the entry based on using both a state of a branch prediction of a stored branch target address stored in the entry being identified and the data processing cycle saving information to determine whether to store the branch target address in the entry.
7. The method of claim 1 further comprising:
storing a branch prediction state of the branch target address in the entry after a change of instruction flow occurs in response to the branch instruction.
8. A data processing system comprising:
a branch target buffer (BTB) having a plurality of entries; and
control logic circuitry coupled to the BTB for determining whether a predetermined branch target address is stored in the BTB, the control logic circuitry identifying an entry in the branch target buffer for allocation to receive the predetermined branch target address in response to a miss in the BTB, the control logic circuitry allocating the entry based upon data processing cycle saving information, the data processing cycle saving information being stored in the data processing system.
9. The data processing system of claim 8 wherein the data processing cycle saving information is stored in the BTB in a field of each entry of the BTB.
10. The data processing system of claim 8 wherein the control logic circuitry further causes a branch prediction state of the branch target address to be stored in the entry after a change of instruction flow occurs in response to the branch instruction.
11. The data processing system of claim 10 wherein the control logic circuitry uses both the data processing cycle saving information and the branch prediction state that are stored in the data processing system to determine allocations in the BTB.
12. The data processing system of claim 8 wherein the control logic circuitry determines the data processing cycle saving information by determining a number of data processing cycles to be saved by using a presently stored branch target address in the entry.
13. The data processing system of claim 8 wherein the control logic circuitry determines the data processing cycle saving information by determining a difference between a savings in data processing cycles obtained by a presently stored target address in the entry and a savings in data processing cycles that would be realized in response to a subsequent access of the branch target address if the branch target address were stored in the BTB.
14. A method for branch target buffer (BTB) allocation in a pipelined data processing system, comprising:
fetching instructions from a plurality of instructions and determining that one of the plurality of instructions is a branch instruction;
determining a branch target address corresponding to the branch instruction;
determining whether the branch target address is stored in a branch target buffer (BTB); and
when the branch target address is not stored in the branch target buffer, identifying an entry in the branch target buffer for allocation to receive the branch target address and based upon a state of a branch prediction of the entry being identified, determining whether to store the branch target address in the entry.
15. The method of claim 14 wherein the state of the branch prediction of the entry being identified is stored in the entry of the branch target buffer.
16. The method of claim 14 further comprising:
determining a state of the branch prediction of the branch target in the entry of the branch target buffer.
17. The method of claim 16 wherein when the state of the branch prediction of the branch target in the entry being identified indicates a not-taken state, allocation of the branch target address into the entry is performed.
18. The method of claim 14 further comprising:
determining whether to allocate the entry in the branch target buffer based upon a number of data processing cycles that would be saved in response to a subsequent access of the branch target address if the branch target address is stored in the entry in the branch target buffer.
19. The method of claim 18 further comprising:
storing the number of data processing cycles that would be saved in the entry of the branch target buffer upon allocation of the entry in the branch target buffer.
20. The method of claim 14 further comprising:
determining whether to allocate the entry in the branch target buffer based upon a difference between a savings in data processing cycles obtained by a presently stored target address in the entry and a savings in data processing cycles that would be realized in response to a subsequent access of the branch target address if the branch target address were stored in the BTB.