Embedded substrate interconnect for underside contact to source and drain regions
View Patent ↗A semiconductor topography ( 10 ) is provided which includes a semiconductor-on-insulator (SOI) substrate having a conductive line ( 16 ) arranged within an insulating layer ( 22 ) of the SOI substrate. A method for forming an SOI substrate with such a configuration includes forming a first conductive line ( 16 ) within an insulating layer ( 22 ) arranged above a wafer substrate ( 12 ) and forming a silicon layer ( 24 ) upon surfaces of the first conductive line and the insulating layer. A further method is provided which includes the formation of a transistor gate ( 28 ) upon an SOI substrate having a conductive line ( 16 ) embedded therein and implanting dopants within the semiconductor topography to form source and drain regions ( 30 ) within an upper semiconductor layer ( 24 ) of the SOI substrate such that an underside of one of the source and drain regions is in contact with the conductive line.
1. An integrated circuit comprising:
a semiconductor-on-insulator (SOI) substrate including a bulk substrate, a semiconductor layer, and an insulating layer disposed between the bulk substrate and the semiconductor layer;
a first conductive line disposed within the insulating layer;
a source region and a drain region within the semiconductor layer, wherein an underside of the source or the drain region contacts the first conductive line;
a isolation region lying adjacent to the source and drain regions; and
a first transistor gate having a portion overlying a portion of the isolation region that overlies a portion of the first conductive line.
2. The integrated circuit of claim 1 , wherein an underside of the other of the source and drain regions is in contact with a different conductive line disposed within the insulating layer.
3. The integrated circuit of claim 1 , further comprising a dielectric layer; wherein a portion of the dielectric layer overlies an entirety of the source and drain regions.
4. The integrated circuit of claim 1 , further comprising:
active regions that include spaced-apart portions of the semiconductor layer, wherein the field isolation region surrounds the active regions, and a portion of the field isolation region overlies the first conductive line; and
a contact structure to the first conductive line, wherein the contact structure extends through the field isolation region and is spaced apart from the active regions.
5. The integrated circuit of claim 4 , wherein:
the active regions include a first active region and a second active region, wherein the first active region includes the source and drain regions; and
an underside of the second active region contacts the first conductive line.
6. The integrated circuit of claim 5 , further comprising a second transistor gate overlying the second active region, wherein the first and second transistor gates are electrically insulating from the first conductive line.
7. The integrated circuit of claim 6 , further comprising a second conductive line and a third conductive wherein:
the second conductive line is spaced apart from the first conductive line and contacts an underside of the second active region; and
the third conductive line is spaced apart from the first and second conductive lines and contacts an underside of the first active region.
8. An integrated circuit comprising:
a substrate;
a first conductive line overlying the substrate;
an insulating layer over the substrate, wherein the insulating layer surrounds the first conductive line;
active regions over portions of the insulating layer, wherein the active regions are spaced apart from each other and the substrate, and wherein the active regions include a first active region;
a field isolation region that surrounds the active regions, wherein a portion of the field isolation region overlies the first conductive line;
a first transistor gate over the first active region;
source and drain regions disposed within the first active region, wherein an underside of the source region or the drain region is in electrical contact with the first conductive line; and
a contact structure to the first conductive line, wherein the contact structure extends through the field isolation region and is spaced apart horn the active regions.
9. The integrated circuit of claim 8 , wherein an underside of the other of the source and drain regions is in contact with a different conductive line disposed within the insulating layer.
10. The integrated circuit of claim 8 , wherein a portion of the first transistor gate overlies a portion of the field isolation region.
11. The integrated circuit of claim 8 , further comprising a dielectric layer, wherein a portion of the dielectric layer overlies an entirety of the source and drain regions.
12. The integrated circuit of claim 8 , wherein:
the active regions further include a second active region; and
an underside of the second active region is in electrical contact with the first conductive line.
13. The integrated circuit of claim 12 , further comprising a second transistor gate overlying the second active region, wherein the first and second transistor gates are electrically insulating horn the first conductive line.
14. The integrated circuit of claim 13 , further comprising a second conductive line and a third conductive wherein:
the second conductive line is spaced apart from the first conductive line and contacts an underside of the second active region; and
the third conductive line is spaced apart from the first and second conductive lines and contacts an underside of the first active region.
15. An integrated circuit comprising:
a substrate;
a first conductive line overlying the substrate;
an insulating layer over the substrate, wherein the insulating layer surrounds the first conductive line;
semiconductor regions spaced apart from each other and the substrate, wherein the semiconductor regions include a first semiconductor region;
forming a field isolation region that surrounds the semiconductor regions, wherein a portion of the field isolation region overlies the first conductive line;
a doped region disposed within the first semiconductor region, wherein the doped region contacts the first conductive line; and
a contact structure contacting the first conductive line, wherein the contact structure extends through the field isolation region and is spaced apart from the semiconductor regions.
16. The integrated circuit of claim 15 , wherein the first conductive line, the insulating layer, and a second conductive line overlie the substrate, and wherein the first and second conductive lines are disposed within the insulating layer.
17. The integrated circuit of claim 15 , further comprising:
a first transistor gate over the first semiconductor region; and
source and drain regions disposed within the first semiconductor region and adjacent to the first transistor gate, wherein the source region or the drain region is electrically coupled to the first conductive line.
18. The integrated circuit of claim 17 , wherein:
the semiconductor regions further include a second semiconductor region; and
an underside of the second semiconductor region contacts the first conductive line.
19. The integrated circuit of claim 18 , further comprising a second transistor gate overlying the second semiconductor region, wherein the first and second transistor gates are electrically insulating from the first conductive line.
20. The integrated circuit of claim 19 , further comprising a second conductive line and a third conductive wherein:
the second conductive line is spaced apart from the first conductive line and contacts an underside of the second semiconductor region; and
the third conductive line is spaced apart from the first and second conductive lines and contacts an underside of the first semiconductor region.