Method of forming a continuous layer of a first metal selectively on a second metal and an integrated circuit formed from the method
View Patent ↗A cap layer for a metal feature such as a copper interconnect on a semiconductor wafer is formed by immersion plating a more noble metal (e.g. Pd) onto the copper interconnect and breaking up, preferably by mechanical abrasion, loose nodules of the noble metal that form on the copper interconnect surface. The mechanical abrasion removes plated noble metal which is only loosely attached to the copper surface, and then continued exposure of the copper surface to immersion plating chemicals leads to plating at new sites on the surface until a continuous, well-bonded noble metal layer has formed. The method can be implemented conveniently by supplying immersion plating chemicals to the surface of a wafer undergoing CMP or undergoing scrubbing in a wafer-scrubber apparatus.
1. A method of forming a continuous layer of a first metal selectively on a second metal, said first metal being more noble than said second metal, the method comprising the steps of:
immersion plating said first metal onto said second metal, and
breaking up nodules of said first metal on the surface of the second metal;
wherein:
during a first time period, immersion plating and breaking up the nodules comprises forming a first set of nodules, such that the first metal is a discontinuous layer, and reducing a height of nodules within the first set of nodules; and
immersion plating and breaking up the nodules are continued after the first time period, such that additional nodules are formed between nodules within the first set of nodules until a continuous layer of the first metal is formed.
2. The method of forming a continuous layer of said first metal on said second metal according to claim 1 , wherein said first metal has greater electronegativity than said second metal.
3. The method of forming a continuous layer of said first metal on said second metal according to claim 1 , wherein the step of breaking up nodules of said first metal comprises performing mechanical abrasion.
4. The method of forming a continuous layer of said first metal on inlaid metal features of a semiconductor wafer, said inlaid metal features being formed of said second metal, according to claim 1 , wherein the steps of immersion-plating and of breaking up nodules are implemented by exposing the inlaid metal feature to immersion plating chemicals suitable for immersion plating said first metal, during chemical mechanical planarization of the wafer layer including said inlaid metal feature.
5. A semiconductor wafer comprising an inlaid feature of a second metal, said inlaid feature having a barrier layer comprising a continuous layer of a first metal, said first metal being more noble than said second metal, said continuous layer being formed by the method of claim 1 .
6. An integrated circuit device comprising an inlaid feature of a second metal, said inlaid feature having a barrier layer comprising a continuous layer of a first metal, said first metal being more noble than said second metal, said continuous noble metal layer being formed by the method of claim 1 .
7. The method of claim 1 , further comprising rotating a pair of brushes in opposite directions while a semiconductor wafer including the second metal is disposed between the pair of brushes.
8. The method of forming a continuous layer of said first metal on said second metal according to claim 2 , wherein said first metal is selected in the group consisting of:
palladium, platinum, ruthenium, silver, gold, rhenium, rhodium, osmium, iridium and nickel.
9. The method of forming a continuous layer of said first metal on inlaid metal features of a semiconductor wafer, said inlaid metal features being formed of said second metal, according to claim 4 , wherein the immersion plating step consists in immersion plating palladium onto an inlaid copper feature.
10. A semiconductor wafer according to claim 5 , wherein said continuous first metal layer is a layer of Pd.
11. A semiconductor wafer according to claim 5 , wherein said inlaid metal feature is a copper feature.
12. An integrated circuit device according to claim 6 , wherein said continuous first metal layer is a layer of Pd.
13. An integrated circuit device according to claim 6 , wherein said inlaid metal feature is a copper feature.
14. The method of claim 7 , further comprising rotating the semiconductor substrate while the semiconductor substrate is disposed between the pair of brushes.