Granted Patent B2

US 7,339,267 · App. 11/140,351 · Granted Mar 4, 2008

Abstract

Claims (38)

1. A method of fabricating a semiconductor package, the method comprising:

providing a semiconductor wafer stack including a plurality of metal pads formed within a first surface of a substrate, an adhesion/plating layer formed on an opposite second surface of said substrate, and a layer of gold formed on a surface of said adhesion/plating layer;

etching said layer of gold in a street area of said semiconductor wafer stack, wherein the etching exposes a plurality of edge portions of said layer of gold, said adhesion/plating layer, and said substrate;

forming an edge seal about said exposed edge portions of said adhesion/plating layer and said layer of gold;

dicing said semiconductor stack in said street area to define a semiconductor die; and

attaching said die to a support structure.

2. A method of fabricating a semiconductor package as claimed in claim 1 , wherein the step of forming an edge seal comprises depositing a layer of barrier metal on said opposite second surface.

3. A method of fabricating a semiconductor package as claimed in claim 2 , wherein the step of depositing a layer of barrier metal comprises sputtering a layer of barrier metal comprised of layers of titanium, nickel-vanadium, and gold, and wherein the gold in the layer of barrier metal has a ratio less than the layer of gold formed on a surface of said adhesion/plating layer.

4. A method of fabricating a semiconductor package as claimed in claim 2 , wherein the layer of barrier metal has a thickness in a range of 1.0 to 1.7 microns.

5. A method of fabricating a semiconductor package as claimed in claim 1 , wherein the support structure is a leadframe.

6. A method of fabricating a semiconductor package as claimed in claim 1 , wherein the step of providing a layer of gold comprises the step of depositing by sputtering a layer of gold on the adhesion/plating layer.

7. A method of fabricating a semiconductor package as claimed in claim 1 , wherein the step of etching includes etching using wet chemistry.

8. A method of fabricating a semiconductor package as claimed in claim 1 , wherein the edge seal prevents the formation of voids in a solder material used during the attaching of said die to a support structure.

9. A method of fabricating a semiconductor package, the method comprising:

providing a semiconductor stack having a plurality of metal pads formed within a first surface of a substrate and a plurality of thermal vias formed in alignment with the plurality of metal pads;

depositing an adhesion/plating layer on an opposite second surface of the substrate and extending into the thermal vias;

depositing a layer of gold on the adhesion/plating layer and extending into the thermal vias;

etching the layer of gold in a street area of the semiconductor stack to expose edges of the layer of gold, the adhesion/plating layer, and the substrate;

forming an edge seal about the exposed edge portions of the layer of gold and the adhesion/plating layer with a layer of barrier metal; dicing the semiconductor stack in the street area; and

soldering the semiconductor stack to a support structure to form the semiconductor package.

10. A method of fabricating a semiconductor package as claimed in claim 9 , wherein the step of etching includes etching using wet chemistry.

11. A method of fabricating a semiconductor package as claimed in claim 9 , wherein the step of forming an edge seal comprises depositing a layer of barrier metal by sputtering, the layer of barrier metal having a thickness in a range of 1.0 to 1.7 microns.

12. A method of fabricating a semiconductor package as claimed in claim 9 , wherein the layer of barrier metal comprises layers of titanium, nickel-vanadium, and gold.

13. A method of fabricating a semiconductor package as claimed in claim 9 , wherein the edge seal prevents leaching of the layer of gold into a solder material used during the soldering process and the formation of voids in the solder material.

14. A method of fabricating a semiconductor package as claimed in claim 9 , wherein the support structure is a leadframe.

15. A semiconductor package comprising:

a semiconductor die comprising:

a substrate having an exposed substrate edge;

at least one metal pad formed within a first surface of the substrate;

an adhesion/plating layer formed on a second surface having an edge portion;

a layer of gold formed on the adhesion/plating layer and having an edge portion;

a layer of barrier metal formed on a surface of the layer of gold, wherein the layer of barrier metal creates and edge seal about the edge portion of the layer of gold and the edge portion of the adhesion/plating layer, the layer of barrier metal extending to the exposed substrate edge and cooperating therewith to form a substantially planar surface; and

a support structure soldered to the semiconductor die.

16. A semiconductor package as claimed in claim 15 , wherein the substrate the exposed substrate edge is longitudinally spaced apart from the edge seal.

17. A semiconductor package as claimed in claim 15 , wherein the support structure is soldered to the semiconductor die with solder material, and wherein the edge seal prevents the leaching of the layer of gold into the solder material.

18. A semiconductor package as claimed in claim 15 , wherein the edge portions of the layer of gold and the adhesion/plating layer are formed during an etch step in a street area of the semiconductor die.

19. A semiconductor package as claimed in claim 15 , wherein the layer of barrier metal is comprised of layers of titanium, nickel-vanadium, and gold, the layer of barrier metal having a thickness in a range of 1.0 to 1.7 microns.

20. A semiconductor package as claimed in claim 15 , further including a plurality of thermal vias formed in the substrate.

Assignments (23)