IP Library Granted Patent US 8,077,803
Granted Patent B2
US 8,077,803 · App. 12/056,652 · Granted Dec 13, 2011

Quarter duty cycle pulse generator for interleaved switching mixer

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Quick Facts
Patent No.
US 8,077,803
App. No.
12/056,652
Granted
Dec 13, 2011
Kind
B2
Abstract

An integrated transmit circuit includes a voltage controlled oscillator ( 702 ) for generating an input frequency signal (e.g., VCO) that is provided to a divide by two quadrature generator circuit ( 706 ) which generates therefrom in-phase and quadrature clocking signals (I, IB, Q, QB) that are applied to control a plurality of transmission gates ( 711 - 718 ) configured in a matched switching topology ( 710 ) so as to selectively pass pulses from the input frequency signal, thereby generating interleaved LO pulses (Ø 1 , Ø 1B , . . . Ø 4 , Ø 4B ). By applying the interleaved LO pulses to control the transmission gates ( 26, 28, 30, 32, 34, 36, 38 , and 40 ) in the upmixer ( 720 ), the +I, −I, +Q, −Q input signals are interleaved over a plurality of phases of a carrier period to produce differential outputs ( 42, 44 ).

Claims (70)

1. A transmitter circuit configured to perform IQ modulation by interleaving in-phase and quadrature signals, comprising:

a baseband stage for generating in-phase and quadrature analog input signals;

a local oscillator pulse generator for generating, comprising:

a frequency dividing quadrature generator circuit that is coupled to receive first and second reference VCO signals and to generate therefrom in-phase and quadrature clocking signals separated in phase from each other by substantially ninety degrees; and

a plurality of transmission gates configured in a matched switching topology so as to selectively pass pulses from the first and second reference VCO signals under control of the in-phase and quadrature clocking signals, thereby generating matched differential interleaved local oscillator signals; and

a switching mixer comprising a plurality of switches for simultaneously receiving the matched differential interleaved local oscillator signals and producing a differential signal by interleaving the in-phase and quadrature analog input signals over a plurality of phases of a carrier period under control of the matched differential interleaved local oscillator signals.

2. The transmitter circuit of claim 1 , where the frequency dividing quadrature generator circuit comprises:

a voltage controlled oscillator circuit for generating first and second VCO signals;

a divide-by-two frequency divider circuit coupled to receive the first and second VCO signals from the voltage controlled oscillator circuit and to generate therefrom first and second reference VCO signals; and

a divide-by-two quadrature generator circuit coupled to receive the first and second reference VCO signals from the divide-by-two frequency divider circuit and to generate therefrom in-phase and quadrature clocking signals separated in phase from each other by substantially ninety degrees.

3. The transmitter circuit of claim 1 , where the frequency dividing quadrature generator circuit comprises:

a voltage controlled oscillator circuit for generating first and second reference VCO signals;

a divide-by-two quadrature generator circuit coupled to receive the first and second reference VCO signals from the voltage controlled oscillator circuit and to generate therefrom in-phase and quadrature clocking signals separated in phase from each other by substantially ninety degrees.

4. The transmitter circuit of claim 1 , where the switching mixer comprises a plurality of transmission gates which are gated by the matched differential interleaved local oscillator signals to interleave the in-phase and quadrature analog input signals by communicating a first in-phase signal at a first phase, communicating a first quadrature phase signal at a second phase, communicating a second in-phase signal at a third phase, and communicating a second quadrature phase signal at a fourth phase.

5. The transmitter circuit of claim 1 , where the local oscillator pulse generator comprises:

a frequency dividing quadrature generator circuit that is coupled to receive first and second reference VCO signals and to generate therefrom in-phase and quadrature clocking signals separated in phase from each other by substantially ninety degrees;

a first transmission gate for generating a first phase local oscillator signal from the second reference VCO signal under control of the in-phase clocking signal;

a second transmission gate for generating a second phase local oscillator signal from the first reference VCO signal under control of the quadrature clocking signal;

a third transmission gate for generating a third phase local oscillator signal from the second reference VCO signal under control of the in-phase clocking signal; and

a fourth transmission gate for generating a fourth phase local oscillator signal from the first reference VCO signal under control of the quadrature clocking signal.

6. The transmitter circuit of claim 5 , where the local oscillator pulse generator comprises:

a fifth transmission gate for generating a complement of the first phase local oscillator signal from the first reference VCO signal under control of the in-phase clocking signal;

a sixth transmission gate for generating a complement of the second phase local oscillator signal from the second reference VCO signal under control of the quadrature clocking signal;

a seventh transmission gate for generating a complement of the third phase local oscillator signal from the first reference VCO signal under control of the in-phase clocking signal; and

an eighth transmission gate for generating a complement of the fourth phase local oscillator signal from the second reference VCO signal under control of the quadrature clocking signal.

7. A method of performing IQ modulation by interleaving in-phase and quadrature signals, comprising:

receiving in-phase and quadrature input signals;

frequency dividing a first VCO reference signal and a second complementary VCO reference signal to generate in-phase and quadrature clocking signals separated in phase from each other by substantially ninety degrees; and

selectively passing pulses from the first VCO reference signal and the second complementary VCO reference signal through a plurality of transmission gates configured in a matched switching topology under control of the in-phase and quadrature clocking signals, thereby generating matched differential interleaved local oscillator signals;

and

applying the matched differential interleaved local oscillator signals to a plurality of switches in a switching mixer for interleaving the in-phase and quadrature input signals over a plurality of phases of a carrier period under control of the matched differential interleaved local oscillator signals to produce a differential signal.

8. The method of claim 7 where frequency dividing the first VCO reference signal and the second complementary VCO reference signal comprises:

receiving first and second VCO signals having a first frequency from a voltage controlled oscillator circuit;

frequency dividing the first and second VCO signals to produce the first VCO reference signal and the second complementary VCO reference signal, each of which has a second frequency which is half of the first frequency; and

generating in-phase and quadrature clocking signals from the first VCO reference signal and the second complementary VCO reference signal, where the in-phase and quadrature clocking signals each have a third frequency which is half of the second frequency such that the in-phase and quadrature clocking signals are separated in phase from each other by substantially ninety degrees.

9. The method of claim 7 where frequency dividing the first VCO reference signal and the second complementary VCO reference signal comprises:

receiving the first VCO reference signal and the second complementary VCO reference signal having a first frequency from a voltage controlled oscillator circuit;

generating in-phase and quadrature clocking signals from the first VCO reference signal and the second complementary VCO reference signal, where the in-phase and quadrature clocking signals each have a second frequency which is half of the first frequency such that the in-phase and quadrature clocking signals are separated in phase from each other by substantially ninety degrees.

10. The method of claim 7 where interleaving the in-phase and quadrature input signals comprises selectively passing pulses from the first VCO reference signal and the second complementary VCO reference signal through a plurality of transmission gates configured in a matched switching topology under control of the in-phase and quadrature clocking signals, thereby communicating a first in-phase signal at a first phase, communicating a first quadrature phase signal at a second phase, communicating a second in-phase signal at a third phase, and communicating a second quadrature phase signal at a fourth phase.

11. The method of claim 7 , where generating matched differential interleaved local oscillator signals comprises:

frequency dividing the first VCO reference signal and the second complementary VCO reference signal to generate a first in-phase clocking signal, a second in-phase clocking signal separated in phase from the first in-phase clocking signal by substantially one hundred and eighty degrees, a first quadrature clocking signal separated in phase from the first in-phase clocking signal by substantially ninety degrees, and a second quadrature clocking signal separated in phase from the first quadrature clocking signal by substantially one hundred and eighty degrees; and

selectively passing pulses from the first VCO reference signal and the second complementary VCO reference signal through a plurality of transmission gates configured in a matched switching topology under control of the first in-phase clocking signal, second in-phase clocking signal, first quadrature clocking signal, and second quadrature clocking signal, thereby generating matched differential interleaved local oscillator signals comprising a first LO pulse signal Ø 1 , a second LO pulse signal Ø 2 , a third LO pulse signal Ø 3 , and a fourth LO pulse signal Ø 4 .

12. The method of claim 11 where selectively passing pulses from the first VCO reference signal and the second complementary VCO reference signal comprises:

applying the first VCO reference signal through a first transmission gate that is controlled by the second in-phase clocking signal to generate a first LO pulse signal Ø 1 ; and

applying the second complementary VCO reference signal through a second transmission gate that is controlled by the second in-phase clocking signal to generate a complementary first LO pulse signal Ø 1B ,

where the first and second transmission gates create substantially no propagation delay between the first LO pulse signal Ø 1 and the complementary first LO pulse signal Ø 1B .

13. The method of claim 7 , where generating matched differential interleaved local oscillator signals comprises

generating a first in-phase clocking signal I with half the frequency of the first VCO reference signal,

generating a second in-phase clocking signal IB separated in phase from the first in-phase clocking signal I by substantially one hundred and eighty degrees,

generating a first quadrature clocking signal Q separated in phase from the first in-phase clocking signal I by substantially ninety degrees,

generating a second quadrature clocking signal QB separated in phase from the first quadrature clocking signal Q by substantially one hundred and eighty degrees,

selectively passing pulses from the first VCO reference signal and the second complementary VCO reference signal through a plurality of transmission gates configured in a matched switching topology under control of the first in-phase clocking signal I, second in-phase clocking signal IB, first quadrature clocking signal Q, and second quadrature clocking signal QB, thereby generating matched differential interleaved local oscillator signals comprising a first set of LO pulse signals and a second set of complementary LO pulse signals such that there is substantially no propagation delay between the first set of LO pulse signals and the second set of complementary LO pulse signals.

14. A method for generating matched differential interleaved local oscillator clock signals, comprising:

generating a first VCO reference signal and a second complementary VCO reference signal;

generating from the first VCO reference signal and the second complementary VCO reference signal a first in-phase clocking signal with half the frequency of the first VCO reference signal, a second in-phase clocking signal separated in phase from the first in-phase clocking signal by substantially one hundred and eighty degrees, a first quadrature clocking signal separated in phase from the first in-phase clocking signal by substantially ninety degrees, and a second quadrature clocking signal separated in phase from the first quadrature clocking signal by substantially one hundred and eighty degrees; and

selectively passing pulses from the first VCO reference signal and the second complementary VCO reference signal through a plurality of transmission gates configured in a matched switching topology under control of the first in-phase clocking signal, second in-phase clocking signal, first quadrature clocking signal, and second quadrature clocking signal, thereby generating matched differential interleaved local oscillator signals comprising a first set of local oscillator pulse signals and a second set of complementary local oscillator pulse signals such that there is substantially no propagation delay between the first set of local oscillator pulse signals and the second set of complementary local oscillator pulse signals.

15. The method of claim 14 , where generating the first VCO reference signal and the second complementary VCO reference signal comprises:

receiving first and second VCO signals having a first frequency from a voltage controlled oscillator circuit; and

frequency dividing the first and second VCO signals to generate the first VCO reference signal and the second complementary VCO reference signal, each of which has a second frequency which is half of the first frequency.

16. The method of claim 14 , where generating the first VCO reference signal and the second complementary VCO reference signal comprises: receiving the first VCO reference signal and the second complementary VCO reference signal having a first frequency from a voltage controlled oscillator circuit.

17. The method of claim 14 , where selectively passing pulses from the first VCO reference signal and the second complementary VCO reference signal comprises:

applying the first VCO reference signal through a first transmission gate that is controlled by at least the first quadrature clocking signal to generate a second LO pulse signal Ø 2 ;

applying the first VCO reference signal through a second transmission gate that is controlled by at least the second quadrature clocking signal to generate a fourth LO pulse signal Ø 4 ;

applying the second complementary VCO reference signal through a third transmission gate that is controlled by at least the first in-phase clocking signal to generate a first LO pulse signal Ø 1 ;

applying the second complementary VCO reference signal through a fourth transmission gate that is controlled by at least the second in-phase clocking signal to generate a third LO pulse signal Ø 3 ;

applying the second complementary VCO reference signal through a fifth transmission gate that is controlled by at least the first quadrature clocking signal to generate a complementary second LO pulse signal Ø 2B ;

applying the second complementary VCO reference signal through a sixth transmission gate that is controlled by at least the second quadrature clocking signal to generate a complementary fourth LO pulse signal Ø 4B ;

applying the first VCO reference signal through a seventh transmission gate that is controlled by at least the first in-phase clocking signal to generate a complementary first LO pulse signal Ø 1B ; and

applying the first VCO reference signal through an eighth transmission gate that is controlled by at least the second in-phase clocking signal to generate a complementary third LO pulse signal Ø 3B .

18. The method of claim 14 , further comprising applying the matched differential interleaved local oscillator clock signals to an interleaved switching upmixer to interleave in-phase and quadrature input signals over a plurality of phases of a carrier period.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
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To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
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To: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
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From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
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From: FREESCALE SEMICONDUCTOR INC.
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To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
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