Method of forming a microelectronic device
View Patent ↗A method of forming a microelectronic device ( 300 ) including the steps of forming a sensor component ( 100 ) and a capping component ( 200 ). The sensor component ( 100 ) includes a sensor structure ( 150, 152 ) and a conductive trace ( 160, 162 ) formed on a first SOI semiconductor wafer ( 110 ). The capping component ( 200 ) includes a plurality of capping layers ( 230, 232 ) formed on a second SOI semiconductor wafer ( 210 ). During fabrication the capping component ( 200 ) is bonded to the sensor component ( 100 ) prior to fabrication of a through hole ( 260 ) in the capping component ( 200 ). Subsequent to bonding the two components together, wafer thinning removes a handle layer ( 112 ) of the first SOI semiconductor wafer ( 110 ) and a handle layer ( 212 ) of the second SOI semiconductor wafer ( 210 ). A through hole ( 260 ) is etched in the capping component ( 200 ) using a buried oxide layer ( 214 ) of the second SOI semiconductor wafer ( 220 ) as a hard mask ( 250 ), thereby exposing the conductive trace ( 160, 162 ) formed as a part of the sensor component ( 100 ).
1. A method of forming a microelectronic device comprising the steps of:
forming a sensor component, comprising a sensor structure and a conductive trace on a first SOI semiconductor wafer;
forming a capping component, comprising a capping layer on a second SOI semiconductor wafer;
bonding the first SOI semiconductor wafer to the second SOI semiconductor wafer such that the sensor structure is enclosed within a microcavity formed between the first and second SOI semiconductor wafers;
wafer thinning the first SOI semiconductor wafer and the second SOI semiconductor wafer subsequent to bonding first SOI semiconductor wafer to the second SOI semiconductor wafer by etching away a handle layer of the first SOI semiconductor wafer and a handle layer of the second SOI semiconductor wafer;
forming a through hole in the capping component to expose the conductive trace formed on the first SOI semiconductor wafer such that the conductive trace is external to the microcavity.
2. A method of forming a microelectronic device as claimed in claim 1 wherein the microelectronic device is a g-cell sensor (accelerometer).
3. A method of forming a microelectronic device as claimed in claim 1 wherein the step of forming a sensor component further includes the step of etching away a sacrificial material formed during fabrication of the sensor structure and the conductive trace to release the sensor structure and the conductive trace.
4. A method of forming a microelectronic device as claimed in claim 1 wherein the capping layer includes an oxide layer and a nitride layer.
5. A method of forming a microelectronic device as claimed in claim 1 wherein the second SOI semiconductor wafer comprises one of an active or sacrificial SOI semiconductor wafer.
6. A method of forming a microelectronic device as claimed in claim 1 wherein the step of bonding the first SOI semiconductor wafer to the second SOI semiconductor wafer includes forming a bonding material comprised of frit glass on a surface of the plurality of capping layers.
7. A method of forming a microelectronic device as claimed in claim 6 wherein the sensor structure is enclosed within a hermetically sealed area formed by the capping component, the bonding material and a surface of a field oxide layer deposited on an uppermost surface of the first SOI semiconductor wafer.
8. A method of forming a microelectronic device as claimed in claim 1 wherein the step of etching away a plurality of handle layers further includes the step of using a buried oxide layer of each of the first and second SOI semiconductor wafers as an etch stop.
9. A method of forming a microelectronic device as claimed in claim 1 wherein the step of forming a through hole further comprises the step of using the buried oxide layer in the second SOI semiconductor as a hard mask during wet etching of the through hole.
10. A method of forming a microelectronic device as claimed in claim 1 wherein the step of forming a through hole in the capping component further includes dry etching the plurality of capping layers to expose the conductive trace and provide for electrical connection.
11. A method of forming a microelectronic device comprising the steps of:
forming a sensor component, comprising a sensor structure and a conductive trace formed on a first wafer, the first wafer including a handle layer, a buried oxide layer and an active layer;
forming a capping component formed on a second wafer, the second wafer including a handle layer, a buried oxide layer;
bonding the first wafer to the second wafer such that the sensor component is enclosed within a microcavity formed between the first and second SOI semiconductor wafers;
etching away the handle layer of the first wafer and the handle layer of the second wafer subsequent to bonding the first wafer to the second wafer; and
etching a through hole in the capping component using the buried oxide layer in the second wafer as a hard mask to expose the conductive trace formed on the first wafer, wherein the conductive trace is external to the microcavity.
12. A method of forming a microelectronic device as claimed in claim 11 wherein the microelectronic device is a g-cell sensor (accelerometer).
13. A method of forming a microelectronic device as claimed in claim 11 wherein the second wafer comprises one of an active or sacrificial SOI semiconductor wafer.
14. A method of forming a microelectronic device as claimed in claim 11 wherein the sensor structure is enclosed within a hermetically sealed area formed by the capping component, the bonding material and a surface of a field oxide layer deposited on an uppermost surface of the first wafer.
15. A method of forming a microelectronic device as claimed in claim 11 wherein the step of etching away the handle layer of the first wafer and the handle layer of the second wafer includes wet etching with tetramethylammonium (TMAH).
16. A method of forming a device comprising the steps of:
forming a sensor component on a first SOI semiconductor wafer;
forming a capping component on a second SOI semiconductor wafer;
bonding the first SOI semiconductor wafer to the second SOI semiconductor wafer; and
wafer thinning the first SOI semiconductor wafer and the second SOI semiconductor wafer subsequent to bonding.
17. A method of forming a device as claimed in claim 16 wherein the step of wafer thinning the first SOI semiconductor wafer and the second SOI semiconductor wafer includes etching away a handle layer of the first SOI semiconductor wafer and a handle layer of the second SOI semiconductor wafer with a wet etch solution and using a buried oxide layer of each of the first and second SOI semiconductor wafers as an etch stop.
18. A method of forming a device as claimed in claim 16 further includes the step of etching a through hole in the capping component subsequent to wafer thinning to expose the conductive trace formed on the first SOI semiconductor wafer.
19. A method of forming a device as claimed in claim 18 wherein the step of etching a through hole further comprises the step of using the buried oxide layer in the second SOI semiconductor as a hard mask during wet etching of the through hole and dry etching the capping layers remaining in the through hole to expose the conductive trace.