Selective interconnect transaction control for cache coherency maintenance
View Patent ↗A data processing system ( 10 ) includes a first master ( 14 ) and a second master ( 16 or 22 ). The first master includes a cache ( 28 ) and snoop queue circuitry ( 44, 52, 54 ) having a snoop request queue ( 44 ) which stores snoop requests. The snoop queue circuitry receives snoop requests for storage into the snoop request queue and provides snoop requests from the snoop request queue to the cache, and the snoop queue circuitry provides a ready indicator indicating whether the snoop request queue can store more snoop requests. The second master includes outgoing transaction control circuitry ( 72 ) which controls initiation of outgoing transactions to a system interconnect. In response to the ready indicator indicating that the snoop request queue cannot store more snoop requests, an initiation hold signal is provided to the outgoing transaction control circuitry to prevent the outgoing transaction control circuitry from initiating any outgoing transactions to the system interconnect ( 12 ) within a subset of transaction types.
1. A data processing system, comprising:
a first master, the first master comprising:
a cache; and
snoop queue circuitry having a snoop request queue which stores snoop requests, the snoop queue circuitry receives snoop requests for storage into the snoop request queue and provides snoop requests from the snoop request queue to the cache, the snoop queue circuitry providing a ready indicator indicating whether the snoop request queue can store more snoop requests; and
a second master, the second master comprising outgoing transaction control circuitry which controls initiation of outgoing transactions to a system interconnect,
wherein in response to the ready indicator indicating that the snoop request queue cannot store more snoop requests,
an initiation hold signal is provided to the outgoing transaction control circuitry to prevent the outgoing transaction control circuitry from initiating any outgoing transactions to the system interconnect within a subset of transaction types wherein the subset of transaction types comprises global write transactions, and
the outgoing transaction control circuitry is configured to initiate all other memory accesses not within the subset of transaction types.
2. The data processing system of claim 1 , further comprising:
an outgoing transaction queue coupled to the outgoing transaction control circuitry, the outgoing transaction queue storing pending outgoing transactions to the system interconnect; and
an outgoing transaction arbiter which arbitrates transactions and provides pending outgoing transactions for storage into the outgoing transaction queue.
3. The data processing system of claim 2 , wherein when the outgoing transaction control circuitry is prevented from initiating any outgoing transactions to the system interconnect within the subset of transaction types, the outgoing transaction control circuitry initiates a transaction to the system interconnect from the outgoing transaction queue that is not within the subset of transaction types.
4. The data processing system of claim 2 , wherein when the outgoing transaction control circuitry is prevented from initiating any outgoing transactions to the system interconnect within the subset of transaction types, the outgoing transaction arbiter re-prioritizes at least one pending outgoing transaction within the outgoing transaction queue.
5. The data processing system of claim 2 , wherein when the outgoing transaction control circuitry receives an asserted grant signal for the system interconnect from a system arbiter which arbitrates accesses to the system interconnect and the initiation hold signal is preventing the outgoing transaction control circuitry from initiating any outgoing transactions to the system interconnect within the subset of transaction types, the initiation hold signal continues to prevent the outgoing transaction control circuitry from initiating any outgoing transactions to the system interconnect within the subset of transaction types regardless of the asserted grant signal.
6. The data processing system of claim 1 , wherein the snoop queue circuitry, after negating the ready indicator to indicate that the snoop request queue cannot store more snoop requests, accepts up to a predetermined number of additional snoop requests only from the first master for storage into the snoop request queue.
7. A method comprising:
snooping a system interconnect to provide snoop requests to a snoop queue of a first master, wherein the snoop queue of the first master provides snoop requests to a cache of the first master;
providing a ready indicator to indicate whether the snoop queue of the first master can receive more snoop requests for storage into the snoop queue; and
in response to the ready indicator indicating that the snoop queue of the first master cannot receive more snoop requests for storage into the snoop queue,
preventing a second master from initiating any transaction within a subset of transaction types to the system interconnect, wherein the subset of transaction types is characterized as only global write transactions, and
allowing the second master to initiate all other memory accesses not within the subset of transaction types.
8. The method of claim 7 , wherein providing the ready indicator comprises:
negating the ready indicator to indicate that the snoop queue cannot receive more snoop requests for storage into the snoop queue; and
after negating the ready indicator, accepting at least one additional snoop request.
9. The method of claim 7 , further comprising:
providing a snoop acknowledge indicator to indicate when a snoop request from the snoop queue has been processed by the cache.
10. The method of claim 7 , further comprising:
the second master receiving an asserted grant signal which grants the second master access to the system interconnect, wherein the preventing the second master from initiating any transaction within the subset of transaction types to the system interconnect is performed regardless of the asserted grant signal.
11. The method of claim 7 , wherein the preventing the second master from initiating any transaction within a subset of transaction types to the system interconnect comprises providing an asserted initiation hold signal to the second master, wherein the second master stops initiating any transaction within the subset of transaction types to the system interconnect in response to the asserted initiation hold signal.
12. A data processing system, comprising:
a system interconnect;
a plurality of masters coupled to the system interconnect, wherein
each master of the plurality of masters comprises a corresponding cache and snoop queue, and
each snoop queue is coupled to provide snoop requests to the corresponding cache;
a cache coherency manager, distinct from the plurality of masters and coupled to the system interconnect, and configured to
provide snoop requests to any snoop queue,
receive a ready indication from any master of the plurality of masters,
provide an initiation hold signal to all other masters of the plurality of masters, wherein
when the master of the plurality of masters provides the ready indicator to the cache coherency manager to indicate that the corresponding snoop queue is full and cannot receive more snoop requests from the cache coherency manager, the cache coherency manager provides the initiation hold signal,
in response to the initiation hold signal, the other masters of the plurality of masters cease initiating any transactions to the system interconnect within a subset of transaction types wherein the subset of transaction types is characterized as only global write transactions, and
further in response to the initiation hold signal, the other masters continue to initiate all other transactions that do not include the subset of transaction types.
13. The data processing system of claim 12 , further comprising:
a system arbiter coupled to the system interconnect to arbitrate accesses on the system interconnect, wherein when the cache coherency manager provides the initiation hold signal, the initiation hold signal continues to prevent the other masters from initiating any transactions to the system interconnect with the subset of transaction types regardless of any grant signal from the system arbiter granting any of the other masters access to the system interconnect.
14. The data processing system of claim 12 , wherein when the cache coherency manager provides the initiation hold signal, any of the other masters initiates a transaction to the system interconnect which is not within the subset of transaction types and the master providing the ready indication initiates any type of transaction to the system interconnect.
15. The data processing system of claim 12 , further comprising:
a third bus master coupled to the system interconnect, wherein the cache coherency manager provides a second initiation hold signal to the third bus master, wherein when the master provides the ready indicator to the cache coherency manager to indicate that the snoop request queue is full and cannot receive more snoop requests from the cache coherency manager, the cache coherency manager also provides the second initiation hold signal to the third master to prevent the third master from initiating any transactions to the system interconnect within the subset of transaction types.