Methods and apparatus for extending semiconductor chip testing with boundary scan registers
View Patent ↗Semiconductor devices, circuits and methods apply both system logic tests and external interface tests via a common series of boundary shift registers residing on the semiconductor chip. In an exemplary embodiment, a test access port receives an external testing signal from a source outside the semiconductor device, and an on-chip test module (e.g. a built-in self-test (BIST) module) contained within the semiconductor device provides an internal testing signal for the system logic. Control logic selectively provides appropriate input testing signals to the boundary shift registers and receives and processes appropriate output signals from the boundary shift registers in each testing mode. Using the various control techniques, a common set of boundary scan registers may be used to implement, for example, an IEEE 1149.1 interface, a BIST isolation wrapper scan chain, a BIST-mode input/output control, or the like.
1. A semiconductor device providing access to system logic via a plurality of interface pins, the device comprising:
an on-chip test module contained within the semiconductor device that is configured to generate an internal testing signal;
a test access port configured to receive an external testing signal from a source outside the semiconductor device;
a plurality of boundary shift registers each coupling one of the plurality of interface pins to the system logic, wherein each of the plurality of boundary shift registers is coupled to the other boundary shift registers by a common serial chain; and
control logic configured to receive the internal testing signal from the built-in self test module and to serially scan the internal testing signal into the plurality of boundary shift registers via the common serial chain in an internal testing mode, and to provide the external testing signal to the plurality of boundary shift registers via the common serial chain in an external test mode to thereby facilitate both internal testing of the system logic and external testing of the interface pins with the common serial chain.
2. The semiconductor device of claim 1 wherein the internal testing signal comprises one of a plurality of built-in self test vectors.
3. The semiconductor device of claim 1 wherein the external testing signal is an IEEE 1149.1 signal.
4. The semiconductor device of claim 1 further comprising a clock generation circuit configured to receive an internal clock signal and an external clock signal from the source external to the semiconductor device, to select one of the internal and external clock signals in response to the internal and external test modes, respectively, and to provide the selected clock signal to each of the plurality of boundary scan registers.
5. The semiconductor device of claim 1 wherein the test access port comprises a design-specific test data register configured to provide a mode select signal in response to data received from the source external to the semiconductor device.
6. The semiconductor device of claim 5 wherein the mode select signal is provided to the control logic to thereby select between the internal test mode and the external test mode.
7. The semiconductor device of claim 1 wherein at least one of the plurality of boundary shift registers is an input cell comprising a multiplexer configured to selectably apply a predetermined signal value to the system logic in the internal test mode.
8. The semiconductor device of claim 1 wherein at least one of the plurality of boundary shift registers is an output cell configured to selectably apply a predetermined signal value to one of the plurality of interface pins in the internal test mode and a serial input signal to the one of the plurality of interface pins in the external test mode.
9. The semiconductor device of claim 1 wherein at least one of the plurality of boundary shift registers is a tri-state buffer control configured to selectably apply a tri-state enable signal to an input/output buffer associated with one of the plurality of interface pins.
10. The semiconductor device of claim 1 wherein at least one of the plurality of boundary shift registers is a bi-directional input-output cell configured to selectably stimulate the system logic with the internal testing signal and to provide a response to the internal testing signal from the system logic via a serial output signal.
11. The semiconductor device of claim 10 wherein the bi-directional input-output cell further comprises a first multiplexer configured to selectably provide internal testing signal to the system logic in response to a control signal provided by the control logic.
12. The semiconductor device of claim 11 wherein the bi-directional input-output cell comprises a second multiplexer configured to selectably place a pre-determined signal value on one of the plurality of interface pins.
13. The semiconductor device of claim 1 wherein the internal testing signal is received from an external device via the test access port.
14. The semiconductor device of claim 1 wherein the plurality of boundary scan registers is configured to form an isolation wrapper around the system logic when in the internal test mode.
15. A bi-directional input/output control circuit for coupling an interface pin on a semiconductor chip to system logic present on the semiconductor chip in response to serial test signals received via a common serial chain from a testing control circuit on the semiconductor chip, the bi-directional input/output control circuit comprising:
an input buffer and an output buffer each coupled to the interface pin;
a bias resistor coupling the input and output buffers to a bias signal; and
a boundary scan register circuit configured to receive the serial test signals from the common serial chain and comprising a buffer control cell configured to provide an enable signal to the output buffer, a bi-directional input-output cell configured to couple the input and output buffers to the system logic, and a resistor control module configured to selectively activate the bias resistor, and wherein the buffer control cell, input-output cell and resistor control module are operable to collectively place the control circuit into an internal test mode and an external test mode in response to the serial test signals, and wherein the bi-directional input-output cell is further configured to apply at least a portion of the serial test signals received via the common serial link to the system logic in the internal test mode and to apply at least a portion of the serial test signals received via the common serial link to the interface pin in the external test mode.
16. The control circuit of claim 15 wherein the bi-directional input/output control circuit is operable to electrically isolate the system logic from the interface pin in response to the serial test signals.
17. The control circuit of claim 15 wherein the bi-directional input/output cell is further configured to obtain output signals from at least one of the system logic in the internal test mode and the interface pin in the external test mode, and to serially provide the output signals to the testing control circuit in response thereto.
18. A method of performing both an internal test and an external test of a semiconductor chip in response to a received input signal, wherein the semiconductor chip comprises a built-in test module, a test access port and a plurality of serially-connected boundary scan registers each associated with one of a plurality of interface pins, the method comprising the steps of:
extracting a testing mode selection signal from the received input signal, the testing mode selection signal having a first value corresponding to the internal test and a second value corresponding to the external test;
generating a plurality of control signals in response to the testing mode selection signal, the plurality of control signals comprising a serial input data signal; and
applying the plurality of control signals to the plurality of boundary scan registers via a common serial chain to thereby apply the serial input data to the system logic with the plurality of boundary scan registers during the internal test and to provide the serial input data to the plurality of interface pins with the plurality of boundary scan registers during the external test, and to receive a serial output signal from the plurality of boundary scan registers via the common serial chain in response to the serial input data in either the internal or external test; and
providing the serial output signal to the built-in self-test module when the testing mode selection signal corresponds to the internal test, and providing the received serial output signal to the test access port when the testing mode selection signal corresponds to the external test.