Circuit having logic state retention during power-down and method therefor
A storage circuit has an input for receiving and storing data, a first power terminal coupled to a first conductor for receiving a first power supply voltage, and a second power terminal coupled to a second conductor. A power gate device has a first terminal coupled to the second conductor, a control terminal for receiving a bias voltage in response to a control signal, and a second terminal coupled to a terminal for receiving a second power supply voltage. A shorting device selectively electrically short circuits the first terminal of the power gate device to the control terminal of the power gate device in response to the control signal, thereby converting the power gate device from a transistor into a diode-connected device. The shorting device is smaller in size than the power gate device.
1. A circuit comprising:
a storage circuit having an input for receiving and storing data and having a first power terminal coupled to a first conductor for receiving a first power supply voltage and having a second power terminal coupled to a second conductor;
a power gate device having a first terminal coupled to the second conductor, a control terminal for receiving a bias voltage in response to a control signal, and a second terminal coupled to a terminal for receiving a second power supply voltage;
a shorting device for selectively electrically short circuiting the first terminal of the power gate device to the control terminal of the power gate device in response to the control signal, thereby converting the power gate device from a transistor into a diode-connected device; and
a logic circuit portion having an input coupled to an output of the storage circuit, the logic circuit portion having a first power terminal coupled to the first conductor and a second power terminal coupled to a third conductor, the storage circuit retaining a state of an input signal to the logic circuit portion when electrical power to the logic circuit portion is gated from at least one of the first power supply voltage and the second power supply voltage in response to the control signal.
2. The circuit of claim 1 further comprising:
an inverter having an input for receiving the control signal and an output for providing the control signal in inverted form that is coupled to the control terminal of the shorting device;
a first transistor having a first current electrode for receiving the first power supply voltage, a control electrode coupled to the output of the inverter for receiving the control signal in inverted form and a second current electrode coupled to the control terminal of the power gate device for providing the bias voltage; and
a second transistor having a first current electrode coupled to the third conductor, a control electrode for receiving the control signal, and a second current electrode coupled to the terminal for receiving the second power supply voltage.
3. The circuit of claim 1 wherein the shorting device further comprises a transistor having a first current electrode connected directly to the first terminal of the power gate device, a control electrode for receiving the control signal, and a second current electrode connected directly to the control electrode of the power gate device.
4. The circuit of claim 3 wherein the control electrode of the shorting device comprises a first width and the control electrode of the power gate device comprises a second width, the first width being no greater than ninety percent of the second width.
5. The circuit of claim 3 wherein the control electrode of the shorting device comprises a first width and the control electrode of the power gate device comprises a second width, the first width being no greater than ten percent of the second width.
6. The circuit of claim 3 wherein the control electrode of the shorting device comprises a first width and the control electrode of the power gate device comprises a second width, the first width being no greater than one percent of the second width.
7. The circuit of claim 1 wherein the power gate device is a footer device for selectively gating a lower magnitude supply voltage of the first power supply voltage and the second power supply voltage to the storage circuit.
8. A method comprising:
providing a storage circuit having an input for receiving and storing data and having a first power terminal coupled to a first conductor for receiving a first power supply voltage, the storage circuit having a second power terminal coupled to a second conductor;
providing a power gate device having a first terminal coupled to the second conductor, a control terminal for receiving a bias voltage in response to a control signal, and a second terminal coupled to a terminal for receiving a second power supply voltage;
selectively electrically short circuiting the first terminal of the power gate device to the control terminal of the power gate device in response to the control signal, thereby converting the power gate device from a transistor into a diode-connected device; and
coupling an input of a logic circuit portion to an output of the storage circuit, the logic circuit portion having a first power terminal coupled to the first conductor and a second power terminal coupled to a third conductor, the storage circuit retaining a state of an input signal to the logic circuit portion when electrical power to the logic circuit portion is gated from at least one of the first power supply voltage and the second power supply voltage in response to the control signal.
9. The method of claim 8 further comprising:
providing an inverter for receiving the control signal, the inverter having an output for providing the control signal in inverted form that is coupled to the control terminal of the shorting device;
providing a first transistor having a first current electrode for receiving the first power supply voltage, a control electrode coupled to the output of the inverter for receiving the control signal in inverted form and a second current electrode coupled to the control terminal of the power gate device for providing the bias voltage; and
providing a second transistor having a first current electrode coupled to the third conductor, a control electrode for receiving the control signal, and a second current electrode coupled to the terminal for receiving the second power supply voltage.
10. The method of claim 8 further comprising:
providing a transistor as the shorting device;
connecting a first current electrode of the transistor directly to the first terminal of the power gate device;
providing a control electrode for receiving the control signal; and
connecting a second current electrode of the transistor directly to the control electrode of the power gate device.
11. The method of claim 10 further comprising:
forming the control electrode of the shorting device to have a first width;
forming the control electrode of the power gate device to have a second width; and
forming the first width to be no greater than ninety percent of the second width.
12. The method of claim 10 further comprising:
forming the control electrode of the shorting device to have a first width;
forming the control electrode of the power gate device to have a second width; and
forming the first width to be no greater than ten percent of the second width.
13. The method of claim 10 further comprising:
forming the current electrode of the shorting device to have a first width;
forming the current electrode of the power gate device to have a second width; and
forming the first width to be no greater than one percent of the second width.
14. The method of claim 8 further comprising:
forming the power gate device as a footer device for selectively gating a lower magnitude supply voltage of the first power supply voltage and the second power supply voltage to the storage circuit.
15. A circuit, comprising:
first, second and third power conductors and a voltage terminal;
a storage circuit comprising a first power terminal coupled to the first power conductor and a second power terminal coupled to the second power conductor;
a first power gate select transistor having a first electrode coupled to the second conductor, a control electrode, and a second electrode coupled to the voltage terminal;
a shorting transistor having a first electrode connected directly to the first electrode of the first power gate select transistor, a control electrode, and a second current electrode connected directly to the control electrode of the first power gate select transistor;
an inverter having an input for receiving a control signal and having an output coupled to the control electrode of the first power gate select transistor for providing the control signal after a logic value inversion;
a biasing transistor coupled to the inverter and the control electrode of the power gate select transistor for providing a bias voltage to the first power gate select transistor in response to the control signal; and
a second power gate select transistor comprising a first current electrode coupled to the third power conductor, a second current electrode coupled to the voltage terminal, and a control electrode for receiving the control signal.
16. The circuit of claim 15 wherein the control electrode of the shorting transistor comprises a first width, the control electrode of the first power gate select transistor comprises a second width, and the first width is no greater than ninety percent of the second width.
17. The circuit of claim 15 wherein the control electrode of the shorting transistor comprises a first width, the control electrode of the first power gate select transistor comprises a second width, and the first width is no greater than ten percent of the second width.
18. The circuit of claim 15 wherein the control electrode of the shorting transistor comprises a first width, the control electrode of the first power gate select transistor comprises a second width, and the first width is no greater than one percent of the second width.