Shared resource based thread scheduling with affinity and/or selectable criteria
View Patent ↗Threads may be scheduled to be executed by one or more cores depending upon whether it is more desirable to minimize power or to maximize performance. If minimum power is desired, threads may be schedule so that the active devices are most shared; this will minimize the number of active devices at the expense of performance. On the other hand, if maximum performance is desired, threads may be scheduled so that active devices are least shared. As a result, threads will have more active devices to themselves, resulting in greater performance at the expense of additional power consumption. Thread affinity with a core may also be taken into consideration when scheduling threads in order to improve the power consumption and/or performance of an apparatus.
1. A method for operating an apparatus having a plurality of processors, comprising:
determining if a thread needs to be executed on one or more of the plurality of processors;
determining if one or more of the plurality of processors is available to execute the thread, and is thus an available processor;
determining if the thread has an affinity for the available processor, wherein said determining if the thread has the affinity for the available processor comprises
counting a number of writes by one or more other threads to a cache associated with the available processor since the thread was last executed on the available processor;
if the thread has the affinity for the available processor, selecting the available processor as a chosen processor to execute the thread;
if the thread does not have the affinity for the available processor, determining a number of active devices;
if the thread does not have the affinity for the available processor, determining if minimize power is selected;
if minimize power is selected, choosing a first processor of the plurality of processors to execute the thread so that the number of active devices is minimized;
if the thread does not have the affinity for the available processor, determining if maximize performance is selected; and
if maximize performance is selected, choosing a second processor of the plurality of processors to execute the thread so that the number of active devices is maximized.
2. A method as in claim 1 , wherein said step of determining the number of active devices comprises:
monitoring one or more power states of the apparatus.
3. A method as in claim 1 , wherein said step of determining the number of active devices comprises:
monitoring one or more performance states of the apparatus.
4. A method as in claim 1 , further comprising:
if the thread has the affinity for the available processor, determining whether the affinity is less than a threshold; and
indicating that the thread does not have the affinity for the available processor if the affinity is less than the threshold.
5. A method as in claim 1 , further comprising:
executing the thread.
6. A method as in claim 1 , wherein the active devices comprise one or more of the plurality of processors.
7. A method as in claim 1 , wherein the active devices comprise one or more caches.
8. A method as in claim 1 , wherein the active devices comprise one or more non-processor circuitry used by the one or more plurality of processors.
9. A method as in claim 1 , wherein the one or more plurality of processors comprise one or more cores executing a same instruction set.
10. An apparatus, comprising:
a plurality of processors; and
control circuitry, coupled to the plurality of processors, said control circuitry comprising:
core availability circuitry for determining if a core is available to execute a thread;
core affinity circuitry for determining if the core has an affinity for the thread, wherein said determining if the core has an affinity for the thread comprises counting a number of writes by one or more other threads to a cache associated with the core since the thread was last executed by the core;
monitoring circuitry for monitoring one or more characteristics of the apparatus; and
select circuitry for selecting one or more of the plurality of processors to execute the thread based on the affinity for the thread and the one or more characteristics of the apparatus.
11. An apparatus as in claim 10 , wherein the control circuitry further comprises:
threshold circuitry for determining whether the affinity for the thread is less than a threshold; and
circuitry indicating that the core does not have the affinity for the thread if the affinity is less than the threshold.
12. An apparatus as in claim 10 , wherein the threshold circuitry comprises:
storage circuitry for storing a power minimization threshold.
13. An apparatus as in claim 10 , wherein the threshold circuitry comprises:
storage circuitry for storing a performance maximization threshold.
14. An apparatus as in claim 10 , further comprising:
a cache, coupled to one or more of the plurality of processors.
15. An apparatus as in claim 14 , wherein the cache is coupled to operate with two or more of the plurality of processors.
16. An apparatus as in claim 10 , wherein the one or more characteristics of the apparatus comprises power usage of the apparatus.
17. An apparatus, comprising:
a plurality of processors; and
control circuitry, coupled to the plurality of processors, said control circuitry comprising:
core availability circuitry for determining if a core is available to execute a thread;
core affinity circuitry for determining if the core has an affinity for the thread, wherein said determining if the core has the affinity for the thread comprises counting a number of writes by one or more other threads to a cache associated with the core since the thread was last executed by the core;
monitoring circuitry for monitoring performance of the apparatus and for monitoring power usage of the apparatus;
select circuitry for selecting one or more of the plurality of processors to execute the thread based on a selection criteria, said selection criteria comprising the affinity for the thread, a performance of the apparatus, and a power usage of the apparatus;
threshold circuitry for determining if the affinity for the thread exceeds a threshold; and
thread scheduling circuitry, coupled to the core availability circuitry, coupled to the core affinity circuitry, coupled to the monitoring circuitry, coupled to the select circuitry, coupled to the monitoring circuitry, coupled to the select circuitry, and coupled to the threshold circuitry, said thread scheduling circuitry scheduling the thread for execution.
18. An apparatus as in claim 17 , wherein the control circuitry comprises a state machine to implement one or more functions of the core availability circuitry, the core affinity circuitry, the monitoring circuitry, the select circuitry, the threshold circuitry, and the thread scheduling circuitry.
19. An apparatus as in claim 17 , wherein the control circuitry comprises software to implement one or more functions of the core availability circuitry, the core affinity circuitry, the monitoring circuitry, the select circuitry, the threshold circuitry, and the thread scheduling circuitry.
20. An apparatus as in claim 17 , wherein the threshold circuitry comprises:
storage circuitry for storing a power minimization threshold; and
storage circuitry for storing a performance maximization threshold.