IP Library Granted Patent US 7,868,393
Granted Patent B2
US 7,868,393 · App. 12/037,280 · Granted Jan 11, 2011

Space efficient integrated circuit with passive devices

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Quick Facts
Patent No.
US 7,868,393
App. No.
12/037,280
Granted
Jan 11, 2011
Kind
B2
Abstract

A multimodal integrated circuit (IC) is provided, comprising, first ( 74 ) and second ( 76 ) semiconductor (SC) devices, and first ( 78 ) and second ( 80 ) integrated passive devices (IPDs) coupled, respectively, to the first ( 74 ) and second ( 76 ) SC devices, wherein the first IPD ( 78 ) overlies the second SC device ( 76 ) and the second IPD ( 80 ) overlies the first SC device ( 74 ) chosen such that the underlying SC device ( 74, 76 ) is not active at the same time as its overlying IPD ( 80, 78 ). By placing the IPDs ( 78, 80 ) over the SC devices ( 76, 74 ) a compact IC layout is obtained. Since the overlying IPD ( 78, 80 ) and underlying SC ( 76, 74 ) are not active at the same time, undesirable cross-talk ( 68, 69 ) between the IPDs ( 78, 80 ) and the SC devices ( 76, 74 ) is avoided. This arrangement applies to any IC having multiple signal paths (RF 1 , RF 2 ) where the IPDs ( 78, 80 ) of a first path (RF 1 , RF 2 ) may be placed over the SC devices ( 76, 74 ) of a second path (RF 2 , RF 1 ) not active at the same time. This is especially useful with high frequencies ICs.

Claims (28)

1. A multimodal integrated circuit, comprising:

first and second semiconductor devices;

first and second integrated passive devices, wherein the first integrated passive device is coupled to the first semiconductor device and the second integrated passive device is coupled to the second semiconductor device; and

wherein the first integrated passive device overlies the second semiconductor device and the second integrated passive device overlies the first semiconductor device and each underlying semiconductor device is not active at the same time as the overlying integrated passive device.

2. The integrated circuit of claim 1 , wherein the integrated passive devices comprise a thin film inductor or thin film capacitor or thin film resistor or a combination thereof.

3. The integrated circuit of claim 1 , wherein the integrated passive devices comprise a filter or transmission line or interconnections or combinations thereof.

4. The integrated circuit of claim 3 , wherein the integrated passive devices comprise a filter having therein an acoustic resonator or micro-electrical-mechanical system resonator or a combination thereof.

5. The integrated circuit of claim 1 , where in the first integrated passive device is serially coupled to the first semiconductor device.

6. The integrated circuit of claim 1 , where in the first integrated passive device is serially coupled to the first semiconductor device ( 74 ) and the second integrated passive device is serially coupled to the second semiconductor device.

7. The integrated circuit of claim 1 , wherein the first and second integrated passive devices are separated from the second and first semiconductor devices by an interlayer dielectric.

8. The integrated circuit of claim 1 , where in the semiconductor devices are field effect transistors.

9. A monolithic integrated circuit, comprising:

a substrate having therein first and second semiconductor devices, each with first and second principal electrodes and a control electrode;

an interlayer dielectric overlying the first and second semiconductor devices; first and second integrated passive devices overlying the interlayer dielectric; and

wherein the first integrated passive device overlies the second semiconductor device and the second integrated passive device overlies the first semiconductor device, configured so that the first and second semiconductor devices are not ON at the same time that their overlying integrated passive device is active.

10. The integrated circuit of claim 9 , wherein the first integrated passive device is coupled to a principal electrode of the first semiconductor device and the second integrated passive device is coupled to a principal electrode of the second semiconductor device.

11. The integrated circuit of claim 9 , wherein the first integrated passive device is serially coupled to the first semiconductor device and the second integrated passive device is serially coupled to the second semiconductor device.

12. The integrated circuit of claim 9 , wherein the integrated passive devices comprise planar inductances, planar capacitances or planar resistances or a combination thereof.

13. The integrated circuit of claim 9 , wherein the integrated passive devices comprise a planar filter, transmission line or interconnections or a combination thereof.

14. The integrated circuit of claim 13 , wherein the integrated passive devices comprise a filter having therein an acoustic resonator or a micro-electrical-mechanical system resonator or a combination thereof.

15. The integrated circuit of claim 9 , wherein semiconductor devices are field effect transistors with control gates and the integrated passive devices overlie the control gates ( 66 ).

16. An electronic structure, comprising:

a substrate; multiple semiconductor devices formed in or on the substrate; and

multiple integrated passive devices formed on the substrate, overlying at least some of the multiple semiconductor devices; arranged so that, when the electronic structure is energized, an overlying integrated passive device and its underlying semiconductor device are not active at the same time.

17. The electronic structure of claim 16 , further comprising an interlayer dielectric located between the overlying integrated passive devices and underlying semiconductor devices.

18. The electronic structure of claim 16 , wherein the integrated passive devices comprise planar inductors.

19. The electronic structure of claim 16 , wherein the semiconductor devices comprise field effect devices.

20. The electronic structure of claim 16 , wherein an integrated passive device overlying a first SC device is electrically coupled to a second semiconductor device different than the first semiconductor device.

Assignments (31)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
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RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Mar 15, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
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SECURITY AGREEMENT Recorded Jul 7, 2008
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 18, 2008
From: HUANG, JENN HWA; GLASS, ELIZABETH C.
To: FREESCALE SEMICONDUCTOR, INC.
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