Power semiconductor device and method of manufacturing a power semiconductor device
View Patent ↗A semiconductor power switch having an array of basic cells in which peripheral regions in the active drain region extend beside the perimeter of the base-drain junction, the peripheral regions being of higher dopant density than the rest of the second drain layer. Intermediate regions in the centre of the active drain region are provided of lighter dopant density than the rest of the second drain layer. This provides an improved compromise between the on-state resistance and the breakdown voltage by enlarging the current conduction path at in its active drain region. On the outer side of each edge cell of the array, the gate electrode extends over and beyond at least part of the perimeters of the base-source junction and the base-drain junction towards the adjacent edge of the die. Moreover, on the outer side of each edge cell, the second drain layer includes a region of reduced dopant density that extends beyond the gate electrode right to the adjacent edge of the die.
1. A vertical insulated gate field-effect transistor semiconductor device comprising:
an array of cells formed in a die of semiconductor material presenting a first face and a second face opposite to said first face, with first and second superposed drain layers of a first conductivity type, the first drain layer extending from said second face and the second drain layer having a less high dopant density than said first drain layer and extending to said first face said array including basic cells and edge cells at the edges of said array,
each of said basic cells comprising a source region of said first conductivity type extending from said first face
a base region of the opposite conductivity type surrounding said source region at and below said first face, said base region forming with said source region and drain layers respectively a base-source junction and a base-drain junction both extending to said first face so as to define respective junction perimeters thereat,
a gate electrode insulated from said die by an insulating layer and extending at said first face over at least part of said perimeters of said base-source junction and said base-drain junction at said first face, whereby to form a conductive channel in an on-state of the device in said base region between said source region and said drain layers in response to a gate voltage applied to said gate electrode; and
an active drain region in said second drain layer at the first face between base regions of adjacent cells, the active drain region comprising:
peripheral regions extending beside respective perimeters of said base-drain junctions not deeper than the base regions, said peripheral regions being of higher dopant density than the rest of said second drain layer and an intermediate region between the peripheral regions in the centre of the active drain region provided with a lighter dopant density than the rest of the second drain layer so as to present to source-drain current a trumpet shaped conductivity path.
2. A semiconductor device as claimed in claim 1 , wherein said intermediate regions in said second drain layer present a reduced dopant density adjacent said first face , at least in the vicinity of said peripheral region.
3. A semiconductor device as claimed in claim 2 further comprising:
edge cells at the edges of said array, each of said edge cells comprising a source region of said first conductivity type extending from said first face and a base region of the opposite conductivity type surrounding said source region at and below said first face , said base region forming with said source region and second drain layer respectively a base-source junction and a base-drain junction both extending to said first face so as to define respective junction perimeters thereat, and a gate electrode insulated from said die and disposed at said first face extending over and beyond at least part of said perimeters of said base-source junction and said base-drain junction at said first face towards the adjacent edge of the die, wherein said second drain layer in each of said cells includes a region of reduced dopant density that extends beyond said gate electrode towards the adjacent edge of the die.
4. A semiconductor device as claimed in claim 1 , wherein said insulating layer is thinner in the vicinity of said junction perimeters than in areas adjacent said intermediate regions .
5. A method of making a vertical insulated gate field-effect transistor semiconductor device, wherein the a vertical insulated gate field-effect transistor semiconductor device includes an array of cells formed in a die of semiconductor material presenting a first face and a second face opposite to said first face, with first and second superposed drain layers of a first conductivity type, the first drain layer extending from said second face and the second drain layer having a less high dopant density than said first drain layer and extending to said first face, said array including basic cells and edge cells at the edges of said array; wherein each of said basic cells comprising: a source region of said first conductivity type extending from said first face, a base region of the opposite conductivity type surrounding said source region at and below said first face, said base region forming with said source region and drain layers respectively a base-source junction and a base-drain junction both extending to said first face so as to define respective junction perimeters thereat, a gate electrode insulated from said die by an insulating layer and extending at said first face over at least part of said perimeters of said base-source junction and said base-drain junction at said first face: whereby to form a conductive channel in an on-state of the device in said base region between said source region and said drain layers in response to a gate voltage applied to said gate electrode, and an active drain region in said second drain layer at the first face between base regions of adjacent cells, the active drain region comprising peripheral regions extending beside respective perimeters of said base-drain junctions not deeper than the base regions, said peripheral regions being of higher dopant density than the rest of said second drain layer and an intermediate region between the peripheral regions in the centre of the active drain region provided with a lighter dopant density than the rest of the second drain layer so as to present to source-drain current a trumpet shaped conductivity path, the method comprising:
producing said second drain layer wherein producing said second drain layer includes growing semiconductor material epitaxially on said first drain layer; and
producing said source and base regions and said peripheral region includes, wherein said producing said source and base regions and said peripheral region includes introducing dopants into said second drain layer and diffusing said dopants therein.
6. A method of making a semiconductor device as claimed in claim 5 wherein the density of dopant in said second layer is reduced during the step of growing semiconductor material epitaxially on said first drain layer.
7. A method of making a semiconductor device as claimed in claim 5 further comprising:
forming a stack including said gate electrode on said first face;
introducing dopant for said peripheral regions into the die from said first face using said stack as masking; and
subsequently introducing dopant for said base and source regions into the die from said first face using said stack as masking.
8. A method of making a semiconductor device as claimed in claim 6 further comprising:
forming a stack including said gate electrode on said first face;
introducing dopant for said peripheral regions into the die from said first face using said stack as masking; and
subsequently introducing dopant for said base and source regions into the die from said first face using said stack as masking.
9. A semiconductor device as claimed in claim 2 , wherein said insulating layer is thinner in the vicinity of said junction perimeters than in areas adjacent said intermediate regions.
10. A semiconductor device as claimed in claim 3 , wherein said insulating layer is thinner in the vicinity of said junction perimeters than in areas adjacent said intermediate regions.