Method and apparatus for handling shared hardware and software debug resource events in a data processing system
View Patent ↗For some data processing systems, it is important to be able to handle overlapping debug events generated by a shared set of debug resources which are trying to cause both exception processing and debug mode entry. However, exception processing and debug mode entry generally have conflicting requirements. In one embodiment, exception priority processing is initially given to the software debug event. Normal state saving is performed and the first instruction of the debug exception handler is fetched, but not executed. Priority is then switched from the software debug event to the hardware debug event and a debug halted state is entered. Once processing of the hardware debug event has been completed, priority is returned to the software debug event and the debug exception handler is executed.
1. A method, comprising:
determining that a software debug event is pending, wherein the software debug event is an event that causes invocation of a software debug interrupt handler to handle the software debug event;
determining that a hardware debug event is pending at a same time that the software debug event is pending, wherein the hardware debug event is an event that causes a processor to cease fetching and executing instructions and to enter a debug halted state;
determining that the pending software debug event initially has priority over the pending hardware debug event;
when the software debug event is being handled, fetching a first instruction of the software debug interrupt handler;
when the software debug event is being handled, executing the first instruction of the software debug interrupt handler;
after said step of fetching the first instruction of the software debug interrupt handler and before said step of executing the first instruction of the software debug interrupt handler, switching priority to the hardware debug event;
handling the hardware debug event between the steps of fetching the first instruction and executing the first instruction; and
after said step of handling the hardware debug event, resuming execution of the software debug interrupt handler for handling of the software debug event.
2. A method as in claim 1 , further comprising:
when the software debug event is being handled, discontinuing instruction issue;
when the software debug event is being handled, proceeding to an instruction boundary; and
when the software debug event is being handled, flushing an instruction pipeline.
3. A method as in claim 2 , further comprising:
selecting the instruction boundary.
4. A method as in claim 3 , wherein selecting the instruction boundary comprises programming a register.
5. A method as in claim 1 , further comprising:
when the software debug event is being handled, saving contents of a program counter.
6. A method as in claim 1 , wherein said step of handling the hardware debug event comprises:
preserving state information;
entering a hardware debug mode;
receiving one or more hardware debug commands via a debug port;
performing the one or more hardware debug commands; and
exiting the hardware debug mode.
7. A method as in claim 6 , wherein said step of entering a hardware debug mode comprises halting the processor.
8. An apparatus, comprising:
a first debug resource for causing a software debug event, the software debug event for causing invocation of a software debug interrupt handler to handle the software debug event;
a second debug resource for causing a hardware debug event, the hardware debug event for causing a processor to cease fetching and executing instructions and to enter a debug halted state; and
circuitry for detecting if the software debug event has occurred and for detecting if the hardware debug event has occurred, said circuitry initially giving priority to the software debug event if both the software debug event and the hardware debug event are pending at a same time, said circuitry beginning handling of the software debug event, said circuitry transferring priority from the software debug event to the hardware debug event after fetching a first instruction for handling the software debug event and before executing the first instruction for handling the software debug event, said circuitry completing handling of the hardware debug event before completing handling of the software debug event.
9. An apparatus as in claim 8 , wherein the first debug resource comprises a first debug register, and wherein the second debug resource comprises a second debug register.
10. An apparatus as in claim 8 , further comprising:
an instruction pipe,
wherein the instruction pipe is flushed during handling of the software debug event.
11. An apparatus as in claim 8 , further comprising:
a program counter register,
wherein a first value of the program counter register is saved in storage circuitry, and wherein a second value is stored in the program counter register,
wherein the first value of the program counter is used during normal operation and wherein the second value is used during handling of the software debug event.
12. An apparatus as in claim 11 , wherein the storage circuitry used to save the first value of the program counter register comprises an exception register.
13. An apparatus as in claim 8 , further comprising:
instruction fetch circuitry for fetching one or more instructions used during handling of the software debug event.
14. An apparatus, comprising:
circuitry for detecting that a software debug event has occurred and for detecting that a hardware debug event has occurred, wherein the software debug event and the hardware debug event are synchronously generated and pending at a same time in response to a processor executing an instruction;
circuitry for initially giving priority to the software debug event;
circuitry for beginning handling of the software debug event;
circuitry for stopping handling of the software debug event and for transferring priority from the software debug event to the hardware debug event after a first instruction for handling the software debug event has been fetched and before the first instruction is executed; and
circuitry for completing handling of the hardware debug event, wherein the first instruction for handling of the software debug event is executed after the handling of the hardware debug event is completed.
15. An apparatus as in claim 14 , wherein the circuitry for transferring priority from the software debug event to the hardware debug event before completing handling of the software debug event comprises a state machine.
16. An apparatus as in claim 15 , wherein the circuitry for initially giving priority to the software debug event if both the software debug event and the hardware debug event have occurred comprises said state machine.
17. An apparatus as in claim 14 , wherein the processor further comprises a program counter for storing a program counter value corresponding to the first instruction before priority is transferred to the circuitry for completing handling of the debug event.
18. An apparatus as in claim 14 , wherein the processor comprises a register for storing an interrupt processing vector, the interrupt processing vector for pointing to a point at which processing is halted after the first instruction is fetched.
19. An apparatus as in claim 14 , wherein the first instruction for the handling of the software debug event is executed after the handling of the hardware debug event is completed and prior to execution of any other instruction after the handling of the hardware debug event is completed.
20. An apparatus as in claim 14 , wherein the apparatus is formed on an integrated circuit.