Hybrid transistor based power gating switch circuit and method
View Patent ↗A method includes forming a first transistor having a first gate dielectric thickness and a first source/drain extension depth, a second transistor having a second gate dielectric thickness and the first source/drain extension depth, and a third transistor having the second gate dielectric thickness and a second source/drain extension depth. The second source/drain extension depth is greater than the first source/drain extension depth. The second gate dielectric thickness is greater than the first gate dielectric thickness. The first transistor is used in a logic circuit. The third transistor is used in an I/O circuit. The second transistor is made without extra processing steps and is better than either the first or third transistor for coupling a power supply terminal to the logic circuit in a power-up mode and decoupling the power supply terminal from the logic circuit in a power-down mode.
1. A method for making an integrated circuit using a semiconductor substrate and for operating the integrated circuit, comprising:
forming a first transistor by:
forming a first gate over a first region of the substrate and on first gate dielectric having a first thickness; and
implanting a first source/drain dopant into the first region using the first gate as a mask while masking the first region;
forming a second transistor by:
forming a second gate over a second region of the substrate and on a second gate dielectric having a second thickness; and
implanting the first source/drain dopant into the second region using the second gate as mask while implanting the first source/drain dopant into the first region;
forming a third transistor by:
forming a third gate over a third region of the substrate and on a third gate dielectric having the second thickness; and
implanting a second source/drain dopant into the third region using the third gate as mask and while masking the first and second regions;
forming a logic circuit using the first transistor having a connection for coupling to a first power supply terminal;
using the second transistor to couple the logic circuit to the first power supply terminal during a power-up mode of the integrated circuit and decouple the logic circuit from the first power supply terminal during a power-down mode of the integrated circuit; and
using the third transistor to interface externally to the integrated circuit.
2. The method of claim 1 wherein the step of implanting the second source/drain dopant is further characterized as being at an energy greater than an energy of the step of implanting the first source/drain dopant and the first source/drain dopant is a same species as the second source/drain dopant.
3. The method of claim 1 wherein:
the step of forming the first transistor further comprises implanting a first species, while masking the third region, that is of a different type from the first source/drain dopant in a portion of the first region under a portion the first gate using the first gate as a mask; and
the step of forming the second transistor further comprises implanting the first species in a portion of the second region under a portion of the second gate using the second gate as a mask while implanting the first species in the portion of the first region.
4. The method of claim 3 , wherein the step of forming the third transistor further comprises performing a halo implant in the third region while masking the first and second regions.
5. The method of claim 1 , wherein the step of using the second transistor is further characterized by the first power supply terminal comprising ground.
6. The method of claim 1 , wherein:
the step of forming the first transistor further comprises forming a first sidewall spacer around the first gate and performing a source/drain implant into the first region using the first sidewall spacer as a mask; and
the step of forming the second transistor further comprises forming a second sidewall spacer around the second gate and performing the source/drain implant into the second region using the second sidewall spacer as a mask while performing the source/drain implant into the first region.
7. The method of claim 6 , wherein the step of forming the third transistor further comprises forming a third sidewall spacer around the third gate and performing the source/drain implant into the third region using the third sidewall spacer as a mask while performing the source/drain implant into the first region.
8. The method of claim 7 , wherein:
the step of forming the first transistor further comprises implanting a first species, while masking the third region, that is of a different type from the first source/drain dopant in a portion of the first region under a portion the first gate using the first gate as a mask; and
the step of forming the second transistor further comprises implanting the first species in a portion of the second region under a portion of the second gate using the second gate as a mask while implanting the first species in the portion of the first region.
9. The method of claim 1 , further comprising:
forming a first well in the first region to a first depth;
forming a second well in the second region to a second depth greater than the first depth; and
forming a third well in the third region to the second depth.
10. The method of claim 1 , wherein the first gate dielectric is formed by:
forming an insulating layer over the first, second, and third regions;
removing the insulating layer from over the first region while leaving the insulating layer over the second and third region; and
forming a dielectric layer on the first region as the first gate dielectric after the step of removing.
11. The method of claim 10 , wherein the steps of forming the second and third transistors are further characterized by the second gate dielectric comprising a first portion of both the dielectric layer and the insulating layer and by the third gate dielectric comprising a second portion of both the dielectric layer and the insulating layer.
12. A method for making an integrated circuit using a semiconductor substrate and for operating the integrated circuit, comprising:
forming a first dielectric layer over a first region of the substrate;
forming a second dielectric layer over a second region and third region of the substrate, wherein the second dielectric layer is thicker than the first dielectric layer;
forming a first gate over the first region and on the first dielectric layer;
forming a second gate over the second region and on the second dielectric layer;
forming a third gate over the third region and on the second dielectric layer;
masking the third region;
performing a first source/drain extension implant into the first region and the second region while masking the third region;
masking the first region and the second region;
performing a second source/drain extension implant into the third region while masking the first region and the second region;
completing forming a first transistor that includes the first gate, a second transistor that includes the second gate, and a third transistor that includes the third gate;
forming a logic circuit using the first transistor having a connection to a first power supply terminal;
using the second transistor to couple the logic circuit to the first power supply terminal during a power-up mode of the integrated circuit and decouple the logic circuit from the first power supply terminal during a power-down mode of the integrated circuit; and
using the third transistor to interface externally to the integrated circuit.
13. The method of claim 12 , further comprising:
masking the third region;
performing a first halo implant on the first and second regions while masking the third region.
14. The method of claim 13 , further comprising performing a second halo implant on the third region while masking the first and second regions.
15. The method of claim 14 , wherein the step of performing the second halo implant is further characterized as being performed at an energy different from that in the step of performing the first halo implant.
16. The method of claim 14 , wherein the step of performing the second source/drain extension implant is further characterized as being performed at a higher energy than the first source/drain extension implant.
17. The method of claim 16 further comprising:
masking the second and third regions;
performing a first well implant into the first region while masking the second and third regions;
masking the first region; and
performing a second well implant into the second and third regions while masking the first region.
18. The method of claim 17 , further comprising:
simultaneously performing a source/drain implant into the first, second, and third regions using the first gate, second gate, and third gate as masks.