Granted Patent B2

US 7,589,658 · App. 12/026,205 · Granted Sep 15, 2009

Abstract

Claims (118)

1. An analog-to-digital converter (ADC) device comprising:

an input terminal to receive an analog signal;

an analog component coupled to the input terminal and comprising:

an amplifier comprising an input and an output; and

a capacitor network coupled to the input and the output of the amplifier, the capacitor network comprising:

a first programmable capacitor comprising a first terminal coupleable to the input terminal and coupleable to the output of the amplifier, and a second terminal coupleable to the input of the amplifier and coupleable to a voltage reference; and

a second programmable capacitor comprising a first terminal coupleable to the input terminal and coupleable to the voltage reference and a second terminal coupleable to the input of the amplifier and coupleable to the voltage reference; and

control logic configured to:

in a first mode, configure the capacitor network and the amplifier in an amplification configuration to amplify the analog signal by a predetermined gain to generate an amplified analog signal; and

in a second mode, configure the capacitor network and the amplifier to generate a series of one or more residue voltages using the amplified analog signal.

2. The ADC of claim 1 , wherein the control logic is configured to:

in the first mode:

configure the first programmable capacitor to a first capacitance and configure the second programmable capacitor to a second capacitance based on the predetermined gain;

at a first phase, configure the capacitor network so as to couple the first terminal of the first programmable capacitor and the first terminal of the second programmable capacitor to the input terminal and to couple the second terminal of the first programmable capacitor and the second terminal of the second programmable capacitor to the voltage reference; and

at a second phase following the first phase, configure the capacitor network so as to couple the first terminal of the first programmable capacitor to the output of the amplifier and couple the second terminal of the first programmable capacitor to the input of the amplifier and to couple the first terminal of the second programmable capacitor to the voltage reference and to couple the second terminal of the second programmable capacitor to the input of the amplifier.

3. The ADC of claim 2 , wherein the control logic is configured to:

in the second mode, configure the first programmable capacitor to a third capacitance and configure the second programmable capacitor to the third capacitance.

4. A method comprising:

receiving a first analog signal at an input terminal of an analog-to-digital converter (ADC);

configuring a capacitor network and an amplifier of the ADC to amplify the first analog signal by a first gain to generate a first amplified analog signal;

configuring the capacitor network and the amplifier to generate a first series of one or more residue voltages based on the first amplified analog signal;

providing for output from the ADC a first digital value based on the first series of one or more residue voltages;

receiving a second analog signal at the input terminal of the ADC;

configuring the capacitor network and the amplifier of the ADC to amplify the second analog signal by a second gain to generate a second amplified analog signal the second gain different than the first gain;

configuring the capacitor network and the amplifier to generate a second series of one or more residue voltages based on the second amplified analog signal; and

providing for output from the ADC a second digital value based on the second series of one or more residue voltages.

5. An analog-to-digital converter (ADC) device comprising:

an input terminal to receive an analog signal;

an analog component coupled to the input terminal and comprising:

an amplifier comprising an input and an output; and

a capacitor network coupled to the input and the output of the amplifier, the capacitor network comprising:

a first capacitor comprising a first terminal coupleable to the input terminal and coupleable to a voltage reference, and a second terminal coupleable to the input of the amplifier and coupleable to the voltage reference;

a second capacitor comprising a first terminal coupleable to the input terminal and coupleable to the output of the amplifier, and a second terminal coupleable to the input of the amplifier and coupleable to the voltage reference;

a third capacitor comprising a first terminal coupleable to the output of the amplifier and coupleable to the voltage reference and a second terminal coupleable to the input of the amplifier and coupleable to the voltage reference; and

a fourth capacitor comprising a first terminal coupleable to the output of the amplifier and coupleable to the voltage reference and a second terminal coupleable to the input of the amplifier and coupleable to the voltage reference; and

control logic configured to:

in a first mode, configure the capacitor network and the amplifier in an amplification configuration to amplify the analog signal by a predetermined gain to generate an amplified analog signal; and

in a second mode, configure the capacitor network and the amplifier to generate a series of one or more residue voltages using the amplified analog signal.

6. The ADC of claim 5 , further comprising:

digital conversion logic coupled to the analog component, the digital conversion logic configured to generate a digital value based on the series of one or more residue voltages.

7. The ADC of claim 5 , wherein the control logic is configured to:

at a first phase of the first mode:

couple the first terminal of the first capacitor and the first terminal of the second capacitor to the input terminal; and

couple the second terminal of the first capacitor and the second terminal of the second capacitor to the voltage reference;

at a second phase of the first mode following the first phase:

couple the first terminal of the first capacitor to the voltage reference;

couple the first terminal of the second capacitor to the output of the amplifier; and

couple the second terminal of the first capacitor and the second terminal of the second capacitor to the input of the amplifier.

8. The ADC of claim 7 , wherein the control logic is configured to:

at the second phase of the first mode:

couple the first terminal of the third capacitor and the first terminal of the fourth capacitor to the output of the amplifier; and

couple the second terminal of the third capacitor and the second terminal of the fourth capacitor to the voltage reference; and

at a third phase of the first mode following the second phase:

couple the first terminal of the third capacitor to the voltage reference;

couple the first terminal of the fourth capacitor to the output of the amplifier; and

couple the second terminal of the third capacitor and the second terminal of the fourth capacitor to the input of the amplifier.

9. An analog-to-digital converter (ADC) device comprising:

a first input terminal to receive a first analog signal;

a second input terminal to receive a second analog signal;

an analog component coupled to the first input terminal and the second input terminal and comprising:

a differential amplifier comprising a first input, a second input, a first input, and a second output; and

a first capacitor network coupled to the first input and the first output of the differential amplifier, the first capacitor network comprising a first plurality of capacitors; and

a second capacitor network coupled to the second input and the second output of the differential amplifier, the second capacitor network comprising a second plurality of capacitors; and

control logic configured to:

in a first mode:

configure the first capacitor network and the differential amplifier in an amplification configuration to amplify the first analog signal by a predetermined gain to generate a first amplified analog signal; and

configure the second capacitor network and the differential amplifier in an amplification configuration to amplify the second analog signal by the predetermined gain to generate a second amplified analog signal; and

in a second mode:

configure the first capacitor network and the differential amplifier to generate a first series of one or more residue voltages using the first amplified analog signal; and

configure the second capacitor network and the differential amplifier to generate a second series of one or more residue voltages using the second amplified analog signal.

10. The ADC of claim 9 , wherein the first analog signal comprises a first signal component of a differential signal and the second analog signal comprises a second signal component of the differential signal.

11. The ADC of claim 9 , wherein the first analog signal comprises a single-ended analog signal and the second analog signal comprises a voltage reference.

12. A method comprising:

receiving an analog signal at an input terminal of an analog-to-digital converter (ADC);

configuring a capacitor network and an amplifier of the ADC to amplify the analog signal by a predetermined gain to generate an amplified analog signal, wherein

configuring the capacitor network and the amplifier comprises:

configuring a first programmable capacitor of the capacitor network to have a first capacitance and configuring a second programmable capacitor of the capacitor network to have a second capacitance based on the select gain;

at a first phase:

coupling a first terminal of the first programmable capacitor and a first terminal of the second programmable capacitor to the input terminal; and

coupling a second terminal of the first programmable capacitor and a second terminal of the second programmable capacitor to a voltage reference; and

at a second phase following the first phase:

coupling the first terminal of the first programmable capacitor and the second terminal of the second programmable capacitor to an input of the amplifier;

coupling the second terminal of the first programmable capacitor to the voltage reference; and

coupling the first terminal of the second programmable capacitor to an output of the amplifier; and

configuring the capacitor network and the amplifier to generate a series of one or more residue voltages based on the amplified analog signal; and

providing for output from the ADC a digital value based on the series of one or more residue voltages.

13. The method of claim 12 , wherein configuring the capacitor network and the amplifier to generate a series of one or more residue voltages based on the amplified analog signal comprises configuring the first programmable capacitor and the second programmable capacitor to each have a third capacitance.

14. A method comprising:

receiving an analog signal at an input terminal of an analog-to-digital converter (ADC);

configuring a capacitor network and an amplifier of the ADC to amplify the analog signal by a predetermined gain to generate an amplified analog signal, wherein

configuring the capacitor network and the amplifier comprises:

at a first phase of the first mode:

coupling a first terminal of a first capacitor of the capacitor network and a first terminal of a second capacitor of the capacitor network to the first input terminal; and

coupling a second terminal of the first capacitor and a second terminal of the second capacitor to a voltage reference;

at a second phase of the first mode following the first phase:

coupling the first terminal of the first capacitor to the voltage reference;

coupling the first terminal of the second capacitor to an output of the amplifier; and

coupling the second terminal of the first capacitor and the second terminal of the second capacitor to an input of the amplifier; and

configuring the capacitor network and the amplifier to generate a series of one or more residue voltages based on the amplified analog signal; and

providing for output from the ADC a digital value based on the series of one or more residue voltages.

15. The method of claim 14 , wherein configuring the capacitor network and the amplifier to amplify the analog signal further comprises:

at the second phase of the first mode:

coupling a first terminal of a third capacitor of the capacitor network and a first terminal of a fourth capacitor of the capacitor network to the output of the amplifier; and

coupling a second terminal of the third capacitor and a second terminal of the fourth capacitor to the voltage reference; and

at a third phase of the first mode following the second phase:

coupling the first terminal of the third capacitor to the voltage reference;

coupling the first terminal of the fourth capacitor to the output of the amplifier; and

coupling the second terminal of the third capacitor and the second terminal of the fourth capacitor to the input of the amplifier.

16. A method comprising:

receiving a first analog signal at a first input terminal of an analog-to-digital converter (ADC);

receiving a second analog signal at a second input terminal of the ADC;

configuring a first capacitor network and an amplifier of the ADC to amplify the first analog signal by a predetermined gain to generate a first amplified analog signal;

configuring a second capacitor network and the amplifier of the ADC to amplify the second analog signal by the predetermined gain to generate a second amplified analog signal;

configuring the first capacitor network and the amplifier to generate a first series of one or more residue voltages based on the first amplified analog signal;

configuring the second capacitor network and the amplifier to generate a second series of one or more residue voltages based on the second amplified analog signal;

providing for output from the ADC a digital value based on the first series of one or more residue voltages and the second series of one or more residue voltages.

17. The method of claim 16 , wherein the first analog signal comprises a first signal component of a differential signal and the second analog signal comprises a second signal component of the differential signal.

18. The method of claim 16 , wherein the first analog signal comprises a single-ended analog signal and the second analog signal comprises a voltage reference.

Assignments (30)