Data processor device supporting selectable exceptions and method thereof
View Patent ↗A processor begins exception processing in response to an exception event. Exception processing by the processor is halted during exception processing to facilitate debugging. The exception event can be a reset exception event or an interrupt exception event. Normal exception processing by the data processor can be resumed after debugging, or exception processing by the data processor can be aborted to allow the normal execution of instructions by the data processor to resume. An exception event can be selectively treated as an interrupt or a reset.
1. A method of an integrated data processor processing exception events comprising:
storing a logic value at a bit of a programmable storage location prior to receipt of a selectable exception, the logic value indicative as to whether selectable exceptions are to be processed as interrupt exceptions or as reset exceptions;
receiving via a first node the selectable exception indicative of an occurrence of a specific selectable exception event;
in response to receiving the selectable exception, invalidating a program counter of the data processor, determining if the selectable exception is to be processed as a reset exception or as an interrupt exception based upon the logic value of the bit stored at the programmable storage location, wherein in response to the logic value being a first value processing the selectable exception as a reset exception, otherwise, in response to the logic value stored at the programmable storage location being a second value processing the selectable exception as an interrupt exception;
receiving via a second node a fixed reset exception indicative of an occurrence of a specific reset exception event; and
processing the fixed reset exception without regards as to the logic value of the bit stored at the programmable storage location.
2. The method of claim 1 wherein processing the selectable exception as the reset exception and processing the selectable exception as the interrupt exception both include invalidating a first set of state information associated with a pipeline of the data processor.
3. The method of claim 2 wherein processing the selectable exception as the reset exception and processing the selectable exception as the interrupt exception both include determining a destination value to be stored at the program counter based upon an interrupt vector associated with the selectable exception.
4. The method of claim 3 wherein processing the selectable exception as the reset exception includes saving at least one of the vector of the selectable exception event or the destination value.
5. The method of claim 2 , wherein processing the selectable exception as the reset exception includes saving a second set of state information associated with the pipeline that is not saved when processing the selectable exception as the interrupt exception.
6. The method of claim 1 wherein upon completion of processing the selectable exception as the reset exception, a portion of the data processor is set at a non-programmable defined state, wherein the data processor is not set at the non-programmable defined state upon completion of processing the selectable exception event as the interrupt exception.
7. The method of claim 6 , further comprising:
in response to completing processing of the selectable exception as the reset exception, beginning processing of application instructions at an address based upon the non-programmable defined state.
8. The method of claim 1 further comprising:
changing the logic value at the bit stored at the programmable storage location subsequent to processing the selectable exception as the reset exception or the interrupt exception, and
repeating receiving via the first node the selectable exception and the said events in response to receiving the selectable exception.
9. A method comprising:
storing a logic value at a bit of a programmable storage location of a data processor;
receiving, via a first node of the data processor, a selectable exception indicative of occurrence of a specific selectable exception event;
determining a first destination address based on the selectable exception;
storing the first destination address at a program counter of the data processor; and
after storing the destination address, processing the selectable exception as a reset exception if the logic value of the bit stored at the programmable storage location has a first value, otherwise, processing the selectable exception as an interrupt exception if the logic value of the bit stored at the programmable storage location has a second value.
10. The method of claim 9 further comprising:
receiving a fixed interrupt exception indicative of an occurrence of a specific fixed interrupt event;
processing the fixed interrupt exception as an interrupt exception without regards as to the logic value of the bit stored at the programmable storage location by executing an interrupt processing routine.
11. The method of claim 9 wherein processing the selectable exception further includes: determining the first destination address based upon an interrupt vector associated with the exception.
12. The method of claim 9 wherein processing the selectable exception further includes: determining the destination address based upon an interrupt vector associated with the selectable exception.
13. The method of claim 9 further comprising:
receiving, via a second node of the data processor, a fixed reset exception indicative of an occurrence of a fixed reset exception; and
processing the fixed event as a reset exception without regards as to the bit value stored at the bit storage location by executing a reset processing routine.
14. The method of claim 9 further comprising:
invalidating the program counter after storing the first destination address if the bit value stored at the bit indicator storage location has a first logic value.
15. The method of claim 9 , wherein of the processing selective exception as a reset exception occurs without regards to the destination address, and processing of the selective exception as an interrupt exception returns control to the pipeline at the destination address.
16. A data processing device comprising:
a bit storage location to store a logic value;
a program counter to store a location of a next address to be executed by a pipeline of a data processor; and
an exception processing module coupled to the storage location, the exception processing module comprising:
a reset exception processing module configured to receive a fixed reset exception at a first node to cause the reset exception processing module to process the reset exception as a fixed reset exception, including setting the program counter to a reset address;
an interrupt exception processing module to set the program counter to an interrupt return address; and
a selectable exception processing module configured to receive a selectable exception at a second node, and to cause the reset exception processing module to process the selectable exception as the reset exception in response to the logic value stored at the bit storage location having a first value, otherwise the selectable exception processing module is to cause the interrupt exception possessing module to process the selectable exception as an interrupt exception in response to the logic value having a second logic value.