Method and apparatus to trace and correlate data trace and instruction trace for out-of-order processors
View Patent ↗In a data processing system, a marked bit is used to identify a data access instruction throughout the pipeline to indicate that the instruction meets user-specified criteria (e.g., a meets a data address range of interest). Based on the marked bit, an in-order program correlation message is generated which indicates when the data access instruction occurs relative to the instruction stream. The marked bit is also used to generate an in-order data trace message. As a result, the trace streams including only data access instructions meeting user-specified criteria may be post-processed and correlated precisely.
1. A method for generating filtered and correlated trace information for an instruction execution stream executed on an out-of-order pipelined processor, comprising:
storing each branch instruction executed by the out-of-order pipelined processor as part of an instruction trace message stream;
marking one or more predetermined store instructions meeting user-specified criteria with at least a marked bit where marking one or more predetermined store instructions comprises setting a marked bit that is associated with a store instruction to identify the store instruction as an interesting data trace event within a specified address range or to identify the store instruction as an interesting data trace event according to a specified debug criteria;
storing an in-order data trace message for each of the predetermined store instructions as part of a data trace message stream, where the data trace message for each predetermined store instruction comprises at least the marked bit;
storing an in-order program correlation message (PCM) for each of the predetermined store instructions that is marked with at least a marked bit as part of the instruction trace message stream, where the program correlation message identifies where each predetermined store instruction occurs in the instruction execution stream, wherein each PCM is stored using a standard PCM message format; and
buffering the data trace message stream and instruction trace message stream in a debug logic circuit.
2. The method of claim 1 , where storing an in-order data trace message comprises generating a data trace message when a load store unit performs a store operation specified by the predetermined store instruction.
3. The method of claim 1 , where storing an in-order program correlation message comprises generating a program correlation message when a completion unit retires a predetermined store instruction that is marked with at least the marked bit.
4. The method of claim 1 , further comprising reconstructing the instruction execution stream based on the data trace message stream and instruction trace message stream.
5. The method of claim 1 , further comprising:
sending the data trace message stream and instruction trace message stream from the debug logic circuit to an external terminal of the out-of-order pipelined processor.
6. The method of claim 1 , further comprising sending the data trace message stream and instruction trace message stream to an external terminal of the out-of-order pipelined processor through a trace port controller.
7. The method of claim 1 , further comprising correlating the data trace message stream and instruction trace message stream.
8. The method of claim 1 , where storing an in-order program correlation message comprises storing a program correlation message using a Nexus Class 3 standard PCM message format.
9. The method of claim 1 , where storing an in-order data trace message comprises:
waiting for each predetermined store instruction to be retired by a completion unit;
generating an in-order data trace message for each predetermined store instruction when a load store unit first attempts to perform the predetermined store instruction.
10. The method of claim 1 , where marking one or more predetermined store instructions meeting user-specified criteria comprises marking one or more predetermined store instructions meeting user-specified debug criteria with at least a marked bit.
11. A data processing system, comprising:
an out-of-order pipelined processor core comprising:
a load store unit for marking predetermined store instructions meeting user-specified debug criteria with at least a marked bit, where marking one or more predetermined store instructions comprises setting a marked bit that is associated with a store instruction to identify the store instruction as an interesting data trace event within a specified address range or to identify the store instruction as an interesting data trace event according to a specified debug criteria,
one or more pipelined stages coupled to receive instructions and data from the load store unit, and a completion unit coupled to receive instructions from the one or more pipelined stages for completing instructions in-order; and
a debug block unit comprising:
a data trace generator for storing an in-order data trace message for each of the predetermined store instructions as part of a data trace message stream, where the data trace message for each predetermined store instruction comprises at least the marked bit, and
a program correlation message (PCM) generator for storing an in-order program correlation message only for each of the predetermined store instructions that is marked with at least a marked bit as part of the instruction trace message stream, where the program correlation message identifies where each predetermined store instruction occurs in the instruction execution stream, wherein each PCM is stored using a standard PCM message format, and
buffering logic operable to assemble the data trace message stream and instruction trace message stream for transmission to an external test debug system.
12. The data processing system of claim 11 , further comprising a trace port controller coupled to the debug block unit core for receiving a stream of data trace messages and program correlation messages from the debug block unit for communication to an external test debug system.
13. The data processing system of claim 11 , where the load store unit marks predetermined store instructions falling within a user-specified data address range with at least a marked bit.
14. The data processing system of claim 13 , where the completion unit finishes each received predetermined store instruction in order and generates program correlation messages for only the predetermined store instructions which are marked with a marked bit.
15. The data processing system of claim 14 , where the completion unit instructs the load store unit to commit each completed store instruction.
16. The data processing system of claim 11 , where the one or more pipelined stages each comprise a storage device for storing the marked bit with each predetermined store instruction as each said predetermined store instruction is sent through the one or more pipelined stages.
17. A method of correlating data and instruction trace streams for an out-of-order processor system, comprising:
assessing a received store instruction at a first pipeline stage for storing data to determine if the store instruction meets a user-specified debug criteria;
marking the store instruction with a data mark bit if the store instruction meets the user-specified debug criteria;
sending the store instruction with a data mark bit through one or more pipelined stages to a second pipeline stage;
completing the store instruction in order at the second pipeline stage and sending a store commit signal to the first pipeline stage upon completing the store instruction;
generating a program correlation message (PCM) at the second pipeline stage only for store instructions having a data mark bit, where the program correlation message identifies where the store instruction occurs in the instruction execution stream and is provided as instruction trace information to a debug logic unit, wherein each PCM is stored using a standard PCM message format;
generating data trace information at the first pipeline stage for the store instruction in response to the store commit signal, where the data trace information for the store instruction comprises at least the data mark bit and where the data trace information is provided to the debug logic unit; and
assembling the data and instruction trace information into data and instruction trace streams at the debug logic unit for transmission to an external test debug system.
18. The method of claim 17 where assembling the data and instruction trace information comprises transferring the data and instruction trace streams through a common message queue to an auxiliary port in the debug logic unit.
19. The method of claim 17 where assessing a received store instruction at a first pipeline stage comprises calculating a first address for the store instruction and comparing the first address to a user-selected address range of interest.