Low noise reference oscillator with fast start-up
View Patent ↗A frequency source having a fast start-up time and low noise in steady state is presented. The frequency source includes an oscillator and a hybrid automatic gain control (AGC) loop that switches between an analog AGC loop at oscillator start up and a digital AGC loop at steady state operation. The analog AGC loop includes a peak detector connected to the oscillator and an error integrator integrating the difference between the peak detector output and a reference voltage. The digital AGC loop includes a comparator comparing the peak detector output and high/low reference voltages, an oscillator counter providing a timer signal, a digital-to-analog converter (DAC) supplied with a digital word, and a low pass filter between the DAC and the oscillator. The timer signal causes a multiplexer to select either the analog AGC loop or the digital AGC loop.
1. A frequency source comprising:
an amplitude-controllable oscillator; and
a hybrid automatic gain control (AGC) loop connected with the oscillator, the hybrid AGC loop comprising an analog AGC loop and a digital AGC loop, the analog AGC loop operable to be connected to the oscillator when the oscillator starts up and the digital AGC loop operable to be connected to the oscillator after the oscillator has reached steady state operation.
2. The frequency source of claim 1 , wherein an output of a peak detector is connected to the analog AGC loop and to the digital AGC loop; and an input of the peak detector is connected to the analog AGC loop and to the digital AGC loop.
3. The frequency source of claim 1 , wherein the oscillator comprises a crystal.
4. The frequency source of claim 1 , wherein the hybrid AGC loop comprises a multiplexer and logic, the logic operable to supply a selection signal to the multiplexer such that the multiplexer selects either the analog AGC loop or the digital AGC loop.
5. The frequency source of claim 1 , wherein the analog AGC loop comprises a peak detector and an error integrator connected with an output of the peak detector and a reference voltage, the error integrator operable to integrate a difference between the output of the peak detector and the reference voltage.
6. The frequency source of claim 1 , wherein the digital AGC loop comprises:
a peak detector operable to detect a peak amplitude of the oscillator,
a comparator connected with an output of the peak detector and a pair of different reference voltages that form a voltage window,
a ripple counter connected with an output of the oscillator and operable to provide a timer signal, and an up/down counter connected with an output of the comparator and operable to provide a digital word,
a digital-to-analog converter (DAC) connected with the ripple counter and the up/down counter and operable to receive the digital word and to be updated by the timer signal, an output of the updated DAC adjusted dependent on the digital word, and
a low pass filter (LPF) connected with an output of the DAC, the oscillator driven dependent on an output of the LPF.
7. The frequency source of claim 1 , further comprising a comparator operable to compare outputs of the analog and digital AGC loops when the oscillator is in start up mode and to supply a feedback signal to the digital AGC loop to adjust the output of the digital AGC loop such that the outputs of the analog and digital AGC loops are approximately the same when the hybrid AGC loop switches driving the oscillator from the analog AGC loop to the digital AGC loop.
8. A frequency source comprising:
an amplitude-controllable oscillator; and
a hybrid automatic am control AGC loop connected with the oscillator, the hybrid AGC boy comprising an analog AGC loop and a digital AGC loop, wherein the hybrid AGC loop is operable to drive the oscillator from the analog AGC loop to the digital AGC loop after a predetermined amount of time.
9. The frequency source of claim 8 , wherein the predetermined amount of time is determined from a set number of oscillations of the oscillator after the oscillations have reached a predetermined threshold.
10. A control circuit comprising:
an analog automatic gain control (AGC) loop;
a digital AGC loop;
a multiplexer operable to select between outputs of the analog and digital AGC loops; and
a first comparator connected with the outputs of the analog and digital AGC loops, the first comparator operable to provide a feedback signal to the digital AGC loop such that the outputs of the analog and digital AGC loops are about the same.
11. The control circuit of claim 10 , wherein the analog AGC loop comprises:
a peak detector operable to detect a peak amplitude of a signal to be measured; and
an error integrator connected with an output of the peak detector and a reference voltage, the error integrator operable to integrate a difference between the output of the peak detector and the reference voltage.
12. The control circuit of claim 10 , wherein the digital AGC loop comprises:
a peak detector operable to detect a peak amplitude of a signal to be measured,
a second comparator connected with an output of the peak detector and a pair of different reference voltages that form a voltage window,
a ripple counter operable to receive the signal to be measured and to provide a timer signal, an output of at least one of the first or second comparator connected with an up/down counter operable to provide a digital word,
a digital-to-analog converter (DAC) connected with the ripple counter and the up/down counter, the DAC operable to receive the digital word and be updated by the timer signal, an output of the updated DAC adjusted dependent on the digital word, and
a low pass filter (LPF) connected with an output of the DAC, the output of the digital loop dependent on an output of the LPF.
13. The control circuit of claim 10 , wherein the multiplexer is operable to switch an output of the multiplexer from the analog AGC loop to the digital AGC loop after a predetermined amount of time from a starting event.
14. The control circuit of claim 10 , wherein an output of the multiplexer is sufficient to drive a crystal oscillator.
15. A method for controlling a crystal oscillator, the method comprising switching between providing an output of an analog automatic gain control (AGC) loop to the oscillator when the oscillator starts up and providing an output of a digital AGC loop to the oscillator after the oscillator has reached steady state operation.
16. The method of claim 15 , further comprising supplying a selection signal to a multiplexer such that the multiplexer selects either the analog AGC loop or the digital AGC loop.
17. The method of claim 15 , wherein the analog AGC loop comprises a peak detector that detects a peak amplitude of the oscillator and an error integrator supplied with an output of the peak detector and a reference voltage, the error integrator integrating a difference between the output of the peak detector and the reference voltage, the oscillator being driven dependent on a result of the integration.
18. The method of claim 15 , wherein the digital AGC loop comprises:
a peak detector that detects a peak amplitude of the oscillator,
a comparator supplied with an output of the peak detector and a pair of different reference voltages that form a voltage window,
a ripple counter to which an output of the oscillator is supplied to provide a timer signal, and an up/down counter to which an output of the comparator is supplied to provide a digital word,
a digital-to-analog converter (DAC) supplied with the digital word and updated by the timer signal, an output of the updated DAC being adjusted dependent on the digital word, and
a low pass filter (LPF) to which an output of the DAC is supplied, the oscillator being driven dependent on an output of the LPF.
19. The method of claim 15 , further comprising comparing outputs of the analog and digital AGC loops when the oscillator is in start up mode and supplying a feedback signal to the digital AGC loop to adjust the output of the digital AGC loop such that the outputs of the analog and digital AGC loops are approximately the same when driving of the oscillator is switched from the analog AGC loop to the digital AGC loop.
20. The method of claim 15 , wherein driving of the oscillator is switched from the analog AGC loop to the digital AGC loop after a predetermined amount of time.