Granted Patent B1

US 7,315,268 · App. 11/453,200 · Granted Jan 1, 2008

Abstract

Claims (66)

1. An integrator circuit, comprising:

an amplifier element configured to receive an input signal at an input node, amplify the input signal, and provide an amplified input signal at an output node;

a feedback capacitor element connected between the output node and the input node; and

a current matching circuit connected to the output node, and configured to sense an output voltage of the amplifier element and to provide a supplemental current to the input node that is less than or equal to a feedback current charging the feedback capacitor element.

2. The integrator circuit, as recited in claim 1 , wherein the supplemental current is substantially equal and opposite in polarity to a feedback current when the output voltage satisfies a set criterion.

3. The integrator circuit, as recited in claim 2 , wherein the set criterion includes one of: having the output voltage rise above a set positive threshold value, and having the output voltage fall below a set negative threshold value.

4. The integrator circuit, as recited in claim 1 , wherein the current matching circuit further comprises:

a first operational amplifier configured to receive the amplifier output signal and a first reference voltage and to provide a first control signal;

a second operational amplifier configured to receive the amplifier output signal and a second reference voltage and to provide a second control signal;

a first transistor connected between a third reference voltage and the input node, the first control signal controlling a conductance of the first transistor; and

a second transistor connected between a fourth reference voltage and the input node, the second control signal controlling a conductance of the second transistor,

wherein the first and second operational amplifiers and the first and second transistors are connected such that the first and second transistors will not both be conductive at the same time.

5. The integrator circuit, as recited in claim 4 ,

wherein the third reference voltage is a greater than or equal to the first reference voltage,

wherein the first reference voltage is greater than the second reference voltage, and

wherein the second reference voltage is greater than or equal to the fourth reference voltage.

6. The integrator circuit, as recited in claim 4 , wherein the first and second transistors are CMOS transistors of different type from each other.

7. An integrator circuit, comprising:

a transconductor configured to receive an input voltage and to provide an output current at an output node;

an integrating capacitor element connected between the output node and a reference voltage, the integrating capacitor element being charged by the output current; and

a current matching circuit connected to the output node, configured to sense an output voltage at the output node and to provide a supplemental current to the output node that is less than or equal to an integrating current charging the integrating capacitor element.

8. The integrator circuit, as recited in claim 7 , wherein the supplemental current is substantially equal and opposite in polarity to an integrating current when the output voltage satisfies a set criterion.

9. The integrator circuit, as recited in claim 8 , wherein the set criterion includes one of: having the output voltage rise above a set positive threshold value, and having the output voltage fall below a set negative threshold value.

10. The integrator circuit, as recited in claim 7 , wherein the current matching circuit further comprises:

a first operational amplifier configured to receive the amplifier output signal and a first reference voltage and to provide a first control signal;

a second operational amplifier configured to receive the amplifier output signal and a second reference voltage and to provide a second control signal;

a first transistor connected between a third reference voltage and the output node, the first control signal controlling a conductance of the first transistor; and

a second transistor connected between a fourth reference voltage and the output node, the second control signal controlling a conductance of the second transistor,

wherein the first and second operational amplifiers and the first and second transistors are connected such that the first and second transistors will not both be conductive at the same time.

11. The integrator circuit, as recited in claim 10 ,

wherein the third reference voltage is a greater than or equal to the second reference voltage,

wherein the second reference voltage is greater than the first reference voltage, and

wherein the first reference voltage is greater than or equal to the fourth reference voltage.

12. The integrator circuit, as recited in claim 10 , wherein the first and second transistors are CMOS transistors of different type from each other.

13. A method of current matching, comprising:

receiving an input signal at an input node of a signal processing element;

performing a signal processing operation on the input signal to provide an output signal at an output node of the signal processing element;

providing a capacitive element between the output node and a reference node;

comparing a voltage across the capacitive element with a first reference voltage;

comparing the voltage across the capacitive element with a second reference voltage;

connecting the output node to a third reference voltage when the voltage across the capacitive element is below the first reference voltage; and

connecting the output node to a fourth reference voltage when the voltage across the capacitive element is above the second reference voltage.

14. The method of current matching, as recited in claim 13 ,

wherein the input signal is an input voltage and the output signal is an output current,

wherein the signal processing operation is a conversion of the input voltage to the output current, and

wherein the reference node is a fifth reference voltage.

15. The method of current matching, as recited in claim 14 , wherein the fifth reference voltage is one of a ground voltage and a negative power supply voltage.

16. The method of current matching, as recited in claim 13 ,

wherein the input signal is an input voltage and the output signal is an output voltage,

wherein the signal processing operation is a voltage amplification process amplifying the input voltage to the output voltage, and

wherein the reference node is the input node.

17. The method of current matching, as recited in claim 13 ,

wherein the third reference voltage is a positive supply voltage, and

wherein the fourth reference voltage is one of a ground voltage and a negative power supply voltage.

18. The method of current matching, as recited in claim 13 ,

wherein the third reference voltage is one of a ground voltage and a negative power supply voltage, and

wherein the fourth reference voltage is a positive supply voltage.

19. The method of current matching, as recited in claim 13 ,

wherein the third reference voltage is greater than or equal to the second reference voltage,

wherein the second reference voltage is greater than the first reference voltage, and

wherein the first reference voltage is greater than or equal to the fourth reference voltage.

20. The method of current matching, as recited in claim 13 ,

wherein the fourth reference voltage is greater than or equal to the second reference voltage,

wherein the second reference voltage is greater than the first reference voltage, and

wherein the first reference voltage is greater than or equal to the third reference voltage.

21. The method of current matching, as recited in claim 13 , wherein the method is implemented in an integrated circuit.

Assignments (30)