IP Library Granted Patent US 7,807,572
Granted Patent B2
US 7,807,572 · App. 11/969,368 · Granted Oct 5, 2010

Micropad formation for a semiconductor

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Quick Facts
Patent No.
US 7,807,572
App. No.
11/969,368
Granted
Oct 5, 2010
Kind
B2
Abstract

A method forms a micropad to an external contact of a first semiconductor device. A stud of copper is formed over the external contact. The stud extends above a surface of the first semiconductor device. The stud of copper is immersed in a solution of tin. The tin replaces at least 95 percent of the copper of the stud and preferably more than 99 percent. The result is a tin micropad that has less than 5 percent copper by weight. Since the micropad is substantially pure tin, intermetallic bonds will not form during the time while the micropads of the first semiconductor device are not bonded. Smaller micropad dimensions result since intermetallic bonds do not form. When the first semiconductor device is bonded to an overlying second semiconductor device, the bond dimensions do not significantly increase the height of stacked chips.

Claims (48)

1. A method comprising:

providing a first semiconductor device having an external contact;

forming a stud of copper over the external contact, wherein the stud extends above a surface of the first semiconductor device; and

immersing the stud of copper in a solution of tin in which the tin replaces at least 95 percent of the copper of the stud resulting in a tin micropad that has less than 5 percent copper by weight.

2. The method of claim 1 , further comprising forming a passivation layer over a top surface of the first semiconductor device having an opening over the external contact.

3. The method of claim 1 , wherein the step of immersing is further characterized by the solution comprising a tin salt solution and a temperature of the solution being within a range of 60 degrees Celsius to 85 degrees Celsius.

4. The method of claim 1 , further comprising:

forming a barrier layer over the external contact prior to the step of forming a stud.

5. The method of claim 4 , further comprising:

forming a passivation layer over a top surface of the first semiconductor device having an opening over the external contact;

wherein the step of forming the barrier layer comprises:

depositing a metal layer over the passivation layer and the external contact prior to forming the stud; and

performing chemical mechanical polishing on the metal layer such that the metal layer is removed over the passivation layer and is retained in the opening.

6. The method of claim 5 , wherein the step of forming the barrier layer further comprises:

recessing the external contact prior to the step of depositing the metal layer, and

wherein forming the barrier layer is further characterized by the barrier layer comprising tantalum.

7. The method of claim 4 , wherein forming the barrier layer comprises electroless plating on the external contact.

8. The method of claim 7 , wherein forming the barrier layer is further characterized by electroless plating comprising immersing the external contact in a bath comprising cobalt.

9. The method of claim 4 , further comprising:

forming a passivation layer over a top surface of the first semiconductor device having an opening over the external contact;

wherein the step of forming the barrier layer comprises:

forming a metal layer over the passivation layer and the external contact prior to the step of forming the stud; and

etching the metal layer using the stud as a mask to leave a portion of the metal layer covered by the stud as the barrier layer.

10. The method of claim 9 , wherein the step of forming the stud is further characterized by forming a copper seed layer after the step of forming the metal layer and prior to the step of etching the metal layer.

11. The method of claim 1 , further comprising:

providing a second semiconductor device having a copper micropad; and

pressing the copper micropad against the tin micropad in an ambient temperature in excess of a melting point of tin.

12. The method of claim 11 , wherein forming the stud is further characterized by:

forming a photoresist layer over the first semiconductor device having an opening over the external contact; and

performing an electroplating step using the photoresist layer as a mask.

13. A method, comprising:

providing a first semiconductor device having a copper stud extending from an external contact above a surface of the first semiconductor device; and

converting the copper stud to a tin micropad that is less than 5 percent copper by weight by immersing the copper stud in a bath of tin salt solution that is within a range of a temperature from 60 degrees Celsius to 85 degrees Celsius.

14. The method of claim 13 , wherein the step of providing the first semiconductor device is further characterized by forming the copper stud by:

forming a photoresist layer over the first semiconductor device having an opening over the external contact; and

performing an electroplating step using the photoresist layer as a mask.

15. The method of claim 13 , further comprising:

providing a second semiconductor device having a copper micropad; and

pressing the copper micropad against the tin micropad in an ambient temperature in excess of a melting point of tin.

16. The method of claim 13 , wherein the step of providing the first semiconductor device is further characterized by the copper stud of the first semiconductor device having a seed layer adjacent to the external contact.

17. The method of claim 16 , wherein the step of providing the first semiconductor device is further characterized by the first semiconductor device having a barrier layer between the seed layer and the external contact.

18. The method of claim 16 , wherein the step of providing the first semiconductor device is further characterized by a barrier layer between and in direct contact with the external contact and the copper stud.

19. A method comprising:

providing a semiconductor device having a surface and a contact that is partially exposed, wherein a portion of the contact that is exposed is recessed lower than the surface;

forming a copper stud extending from an external contact above a surface of the semiconductor device; and

converting the copper stud to a tin micropad that is at least ninety-nine percent tin by weight by immersing the copper stud in a bath of tin-containing solution that is at a temperature within a range of 60 degrees Celsius to 85 degrees Celsius.

20. The method of claim 19 further comprising:

forming a tantalum barrier layer between the contact and the copper stud to prevent penetration of copper and tin into the contact from above.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0688 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →