Adjustable pipeline in a memory circuit
View Patent ↗A technique for operating a memory circuit that improves performance of the memory circuit and/or power consumption for at least some operating points of the memory circuit includes adjusting a number of operational pipeline stages at least partially based on an operating point of the memory. In at least one embodiment of the invention, a method for operating a memory circuit includes selecting a mode of operating the memory circuit at least partially based on a feedback signal generated by the memory circuit. The technique includes operating the memory circuit using a number of pipeline stages based on the selected mode of operation of the memory circuit. In at least one embodiment of the invention, the technique includes sensing a timing margin associated with an individual pipeline stage and generating the feedback signal based thereon.
1. A method of operating a memory circuit comprising:
selecting a mode of operating the memory circuit at least partially based on a feedback signal generated by the memory circuit; and
operating the memory circuit using a number of pipeline stages, the number of pipeline stages being based on the selected mode of operation of the memory circuit.
2. The method, as recited in claim 1 , further comprising:
sensing a timing margin associated with an individual circuit portion of the memory circuit and generating the feedback signal based thereon.
3. The method, as recited in claim 1 , wherein the mode of operation is selected partially based on at least one entry of a table of mode of operation information corresponding to values of at least one of frequency of a control clock signal of the memory circuit and level of a power supply voltage of the memory circuit.
4. The method, as recited in claim 3 , wherein the mode of operation information is based on at least one of the group consisting of a target latency of the memory circuit and a target power consumption of the memory circuit corresponding to the at least one of frequency of the control clock signal and level of the power supply voltage.
5. The method, as recited in claim 1 , wherein the mode of operation is selected further based on magnitude and direction of change of the mode of operation.
6. The method, as recited in claim 1 , wherein the mode of operation is selected based on an instruction at least partially executed by one or more instruction processing units coupled to the memory circuit.
7. The method, as recited in claim 1 , wherein the mode of operation is selected based on configuration information received from at least a pin of an integrated circuit including the memory circuit.
8. The method, as recited in claim 1 , further comprising:
comparing an operating point to at least one threshold value and generating an indicator based thereon,
wherein the mode of operation is selected based on the indicator.
9. The method, as recited in claim 1 , wherein operating the memory circuit using the number of pipeline stages comprises:
providing results of a first circuit portion to a second circuit portion synchronously with respect to a control clock signal when the number of pipeline stages is a first number; and
providing results of the first circuit portion to the second circuit portion asynchronously with respect to the control clock signal when the number of pipeline stages is a second number.
10. The method, as recited in claim 1 , wherein operating the memory circuit using the number of pipeline stages comprises selectively configuring at least one state element to be transparent at least partially based on the number of pipeline stages.
11. The method, as recited in claim 10 , wherein the at least one state element includes a latch circuit.
12. An integrated circuit comprising:
a memory circuit; and
a control circuit configured to select a mode of operation of the memory circuit at least partially based on a feedback signal generated by the memory circuit,
wherein the memory circuit is configured to operate with a number of pipeline stages based on the selected mode of operation of the memory circuit.
13. The integrated circuit as recited in claim 12 , wherein the feedback signal is indicative of timing margin associated with an individual circuit portion of the memory circuit.
14. The integrated circuit as recited in claim 12 , further comprising:
a second memory circuit coupled to the control circuit and configured to store mode of operation information corresponding to values of at least one of the group consisting of frequency of a control clock signal of the memory circuit and level of a power supply voltage of the memory circuit,
wherein the control circuit is configured to select the mode of operation partially based on contents of the second memory circuit corresponding to a particular frequency of the control clock signal and a particular level of the power supply voltage.
15. The integrated circuit as recited in claim 14 , wherein the contents of the second memory circuit are based on at least one of the group consisting of a target latency of the memory circuit and a target power consumption of the memory circuit corresponding to the particular frequency of the control clock signal and the particular level of the power supply voltage.
16. The integrated circuit as recited in claim 12 , wherein the control circuit comprises at least one instruction processing unit configured to select the mode of operation at least partially based on at least partial execution of an instruction of a program executing on the integrated circuit.
17. The integrated circuit as recited in claim 12 , wherein the memory circuit comprises:
a first sense amplifier circuit configured to sense at least one of a plurality of bits from a memory array in response to a sense amplifier enable signal synchronous to a memory clock signal; and
a second sense amplifier configured to sense a bit from at least one of the plurality of bits from the memory array in response to a delayed version of the sense amplifier enable signal and generate the feedback signal based on a differential voltage value generated at the output of the second sense amplifier.
18. The integrated circuit as recited in claim 12 , wherein the memory circuit comprises:
a first circuit portion;
a second circuit portion; and
a third circuit portion coupled between the first and second circuit portions and configurable in a first mode of operation and a second mode of operation,
wherein in the first mode of operation, the third circuit portion receives results of the first circuit portion and provides the results of the first circuit portion as operands to the second circuit portion asynchronously with respect to a clock signal, thereby configuring the first and second circuit portions in the same pipeline stage, and
wherein in the second mode of operation, the third circuit portion latches the results of the first circuit portion and provides the results of the first circuit portion as operands to the second circuit portion synchronously with respect to a transition of the clock signal, thereby configuring the first and second circuit portions in different pipeline stages.
19. The integrated circuit as recited in claim 18 , wherein the first circuit portion comprises a memory word-line and column decode circuit and a memory data acquisition circuit and the third circuit portion comprises a memory line selection circuit.
20. The integrated circuit as recited in claim 18 , wherein at least one of the first, second, and third circuit portions comprises a dynamic logic circuit.
21. An apparatus comprising:
means for providing contents of an array of storage elements using a number of pipeline stages; and
means for selecting a mode of operation of the means for providing at least partially based on a feedback signal generated by a means for providing,
wherein the number of pipeline stages is based on a mode of operation of the means for providing,
wherein the feedback signal is indicative of timing margin associated with an individual circuit portion of the memory circuit.
22. The method as recited in claim 1 , wherein the memory circuit comprises the number of pipeline stages.
23. The apparatus as recited in claim 12 , wherein the memory circuit comprises the number of pipeline stages.
24. The method as recited in claim 21 , wherein the means for providing comprises the number of pipeline stages.