System and method for reducing power consumption of memory in an I/O controller
View Patent ↗A memory system for an I/O controller which includes a memory with multiple memory blocks, a supply voltage control circuit providing power to each memory block, and control logic. Each memory block retains stored information with reduced power consumption when receiving a reduced voltage level. The control logic allocates buffers in the memory and controls the supply voltage control circuit to provide the full voltage level to at least one memory block of at least one allocated buffer and to provide the reduced voltage level to remaining memory blocks. Each memory block includes one or more buffers. In various embodiments the control logic fully powers each memory block of a buffer or less than all of the memory blocks. A linked buffer structure may be used to reduce the memory blocks of an allocated buffer receiving full power, such as only one memory block in the buffer.
1. A memory system for an input/output controller, comprising:
a memory comprising a plurality of memory blocks each having a corresponding one of a plurality of source voltage inputs, wherein each of said plurality of memory blocks performs transfer operations when its source voltage input is at a full voltage level and retains stored information with reduced power consumption when its source voltage input is at a reduced voltage level;
a supply voltage control circuit having a plurality of outputs, each said output coupled to a corresponding one of said plurality of source voltage inputs of said memory, wherein each of said plurality of outputs provides either one of said full voltage level and said reduced voltage level; and
control logic which allocates buffers in said memory to perform transfer operations based on input/output protocol, and which controls said supply voltage circuit to provide said full voltage level to at least two allocated memory blocks which includes at least one memory block of at least one allocated buffer and to provide said reduced voltage level to remaining memory blocks.
2. The memory system of claim 1 , wherein said control logic allocates a buffer comprising at least two memory blocks, and wherein said control logic controls said supply voltage control circuit to provide said full voltage level to less than all of said at least two memory blocks of said allocated buffer.
3. The memory system of claim 2 , wherein said control logic controls said supply voltage control circuit to provide said full voltage level to only one of said at least two memory blocks of said allocated buffer at a time.
4. The memory system of claim 1 , wherein said control logic organizes said plurality of memory blocks into a plurality of buffer blocks in which each buffer block is associated with at least one of said plurality of memory blocks, wherein said control logic allocates a buffer and dynamically links a buffer block into said allocated buffer as needed, and wherein said control logic causes said supply voltage control circuit to provide said full supply voltage to each of said plurality of memory blocks associated with each one of said plurality of buffer blocks newly linked into said allocated buffer.
5. The memory system of claim 4 , wherein said control logic causes said supply voltage control circuit to provide said reduced supply voltage to each of said plurality of memory blocks associated with a last one of said plurality of buffer blocks in said allocated buffer after linking a new buffer block.
6. The memory system of claim 4 , wherein said control logic determines an end of a current buffer block in said allocated buffer during usage, follows a link to a next buffer block of said allocated buffer, causes said supply voltage control circuit to provide said full supply voltage to each of said plurality of memory blocks associated with said next buffer block, and causes said supply voltage control circuit to provide said reduced supply voltage to each of said plurality of memory blocks associated with said current buffer block.
7. The memory system of claim 4 , wherein said input/output protocol indicates a new read or write transfer operation using said allocated buffer, wherein said control logic dynamically links a new buffer block into said allocated buffer to perform said new read or write transfer operation, and wherein said control logic causes said supply voltage control circuit to provide said full supply voltage to said new buffer block and to provide said reduced supply voltage to a last buffer block in said allocated buffer.
8. The memory system of claim 1 , wherein said control logic allocates a buffer comprising multiple memory blocks, and wherein said control logic controls said supply voltage control block to provide said full voltage level to each of said multiple memory blocks of said allocated buffer and to provide said reduced voltage level to at least one memory block of said memory.
9. A integrated input/output controller, comprising:
an embedded memory comprising a plurality of memory blocks each having a corresponding one of a plurality of source voltage inputs, wherein each of said plurality of memory blocks operates at a full voltage level and retains stored information with reduced power consumption when its source voltage input is at a reduced voltage level which is less than said full voltage level;
a memory power control circuit comprising a plurality of outputs, each said output coupled to a corresponding one of said plurality of source voltage inputs of said embedded memory, wherein each of said plurality of outputs provides either one of said full voltage level and said reduced voltage level; and
a controller which allocates buffers in said embedded memory for transfer operations according to input/output protocol, and which controls said memory power control circuit to provide said full voltage level to at least two allocated memory blocks which includes at least one memory block of at least one allocated buffer and to provide said reduced voltage level to remaining memory blocks.
10. The integrated input/output controller of claim 9 , wherein said memory power control circuit comprises:
a power control register storing a plurality of bits indicating which of said plurality of memory blocks receive said full voltage level and which of said plurality of memory blocks receive said reduced voltage level; and
a supply voltage control circuit having an input coupled to said power control register and a plurality of outputs providing either one of said full voltage level and said reduced voltage level based on said plurality of bits of said register.
11. The integrated input/output controller of claim 9 , wherein said controller comprises buffer control logic which allocates a buffer for a pending memory operation, which selects at least one of said plurality of memory blocks included in said allocated buffer, and which programs said memory power control circuit.
12. The integrated input/output controller of claim 11 , wherein said buffer control logic controls said memory power control circuit to provide said full voltage level to each of said plurality of memory blocks included in said allocated buffer.
13. The integrated input/output controller of claim 11 , wherein said buffer control logic controls said memory power control circuit to provide said full voltage level to less than all of said plurality of memory blocks included in said allocated buffer.
14. The integrated input/output controller of claim 13 , wherein said buffer control logic employs a linked buffer structure to identify only one of said memory blocks of said allocated buffer included in a pending memory operation, wherein said buffer control logic controls said memory power control circuit to provide said full voltage level to said identified memory block and to provide said reduced voltage level to every other memory block of said allocated buffer.
15. A method of reducing power consumption of a memory of an input/output controller, comprising:
providing a memory with a plurality of memory blocks each having a corresponding one of a plurality of source voltage inputs, wherein each memory block operates at a full voltage level and retains stored information with reduced power consumption when its source voltage input is at a reduced voltage level which is less than the full voltage level;
allocating buffers based on input/output protocol; and
providing voltage including providing the full voltage level to at least two allocated memory blocks which includes at least one memory block of at least one allocated buffer and providing the reduced voltage level to remaining memory blocks.
16. The method of claim 15 , wherein said allocating comprises allocating a buffer which includes at least one of the plurality of memory blocks and wherein said providing power comprises providing the full voltage level to each memory block included in the allocated buffer.
17. The method of claim 15 , wherein said selecting comprises allocating a buffer which includes at least two of the plurality of memory blocks and wherein said providing voltage comprises providing the full voltage level to less than all of the memory blocks included in the allocated buffer.
18. The method of claim 15 , further comprising:
organizing the plurality of memory blocks into a plurality of buffer blocks in which each buffer block is associated with at least one memory block;
wherein said allocating comprises allocating a buffer and dynamically linking a buffer block into the allocated buffer as needed;
wherein said providing voltage comprises providing the full supply voltage to each memory block associated with each buffer block newly linked into the allocated buffer.
19. The method of claim 18 , further comprising providing the reduced supply voltage to each memory block associated with a last buffer block in the allocated buffer after linking a new buffer block.
20. The method of claim 18 , further comprising:
determining a new read or write transfer operation using the allocated buffer;
dynamically linking a new buffer block into the allocated buffer to perform the new read or write transfer operation;
providing the full supply voltage to each memory block associated with the new buffer block; and
providing the reduced supply voltage to each memory block associated with a last buffer block in the allocated buffer.
21. The method of claim 18 , further comprising:
determining an end of a current buffer block in the allocated buffer during usage;
following a link to a next buffer block of the allocated buffer;
providing the full supply voltage to each memory block associated with the next buffer block; and
providing the reduced supply voltage to each memory block associated with the current buffer block.
22. The method of claim 18 , further comprising:
deallocating the buffer; and
providing the reduced supply voltage to each memory block associated with each buffer block included in the deallocated buffer.