ESD protection for passive integrated devices
View Patent ↗Methods and apparatus are provided for ESD protection of integrated passive devices (IPDs). The apparatus comprises one or more IPDs having terminals or other elements potentially exposed to ESD transients coupled by charge leakage resistances having resistance values much larger than the ordinary impedance of the IPDs at the operating frequency of interest. When the IPD is built on a semi-insulating substrate, various elements of the IPD are coupled to the substrate by spaced-apart connections so that the substrate itself provides the high value resistances coupling the elements, but this is not essential. When applied to an IPD RF coupler, the ESD tolerance increased by over 70%. The invented arrangement can also be applied to active devices and integrated circuits and to IPDs with conductive or insulating substrates.
1. An integrated apparatus with ESD protection, comprising:
one or more passive elements having portions potentially exposed to ESD transients; and
one or more charge leakage resistances extending between the portions potentially exposed to ESD transients, wherein the resistances have values much larger than the impedance of the one or more passive elements at their normal operating frequency.
2. The apparatus of claim 1 , wherein the one or more passive elements are formed on a semi-insulating substrate, and wherein the apparatus further comprises electrical leads coupling the portions potentially exposed to ESD transients to spaced-apart contacts on the semi-insulating substrate, such that the charge leakage resistances are formed by the substrate resistance between the spaced-apart contacts.
3. The apparatus of claim 1 , wherein the one or more passive elements are formed on an insulating substrate, and wherein the apparatus further comprises:
a high resistivity layer formed on the substrate beneath the one or more passive elements; and
electrical leads coupling the portions potentially exposed to ESD transients to spaced-apart contacts on the high resistivity layer such that the charge leakage resistances are formed by the layer resistance between the spaced-apart contacts.
4. The apparatus of claim 1 , wherein the one or more passive elements are formed over a conductive substrate, and wherein the apparatus further comprises:
an insulating layer on the substrate electrically isolating the elements from the substrate;
a high resistivity layer formed on the insulating layer beneath the one or more passive elements; and
electrical leads coupling the portions potentially exposed to ESD transients to spaced-apart contacts on the high resistivity layer such that the charge leakage resistances are formed by the layer resistance between the spaced-apart contacts.
5. The apparatus of claim 1 , wherein the charge leakage resistances are at least about 100 times larger than the impedance of the apparatus at its normal operating frequency of interest.
6. The apparatus of claim 5 , further comprising an active device having at least one terminal coupled to the one or more charge leakage resistances.
7. The apparatus of claim 1 , wherein the charge leakage resistances are at least about 500 times larger than the impedance of the apparatus at its normal operating frequency of interest.
8. The apparatus of claim 1 , wherein the charge leakage resistances are at least about 1000 times larger than the impedance of the apparatus at its normal operating frequency of interest.
9. An ESD protected integrated electronic apparatus, comprising:
an inductor;
a capacitor coupled to the inductor;
two terminals coupled to the inductor and the capacitor; and
one or more charge leakage resistances coupled between the two terminals and having values at least about 100 times larger than the impedance of the apparatus as measured between the two terminals at its normal operating frequency.
10. The apparatus of claim 9 wherein the one or more charge leakage resistances have values at least about 1000 times larger than the impedance of the apparatus as measured between the two terminals at its normal operating frequency.
11. The apparatus of claim 9 wherein at least one of the one or more charge leakage resistances is coupled to the inductor.
12. The apparatus of claim 9 wherein at least one of the one or more charge leakage resistances is coupled to the capacitor.
13. The apparatus of claim 9 wherein at least one of the one or more charge leakage resistances is coupled between the two terminals.