State retaining power gated latch and method therefor
View Patent ↗A circuit has first latch, a second latch, a coupling circuit, and a power down circuit. The first latch has an input/output coupled to a data node. The second latch has an input/output. The coupling circuit is coupled between the input/output of the second latch and the data node. The coupling circuit is enabled during a normal operation of the circuit and disabled during a power down mode of the circuit. The power down control circuit is for disabling the first latch during the power down mode and for a time period after a transition from the power down mode to the normal operation. This allows the second latch to set the state of the first latch when transitioning from the power down mode to the normal mode. Thus normal operation can be fast, and the power down mode can have low leakage current.
1. A circuit, comprising:
a first latch having an input/output coupled to a data node, a clock terminal for receiving a clock signal, and a control terminal for receiving a control signal;
a second latch having an input/output and a clock terminal for receiving the clock signal;
a coupling circuit is coupled between the input/output of the second latch and the data node and is enabled during a normal operation of the circuit and disabled during a power down mode of the circuit; and
a power down control circuit for providing the control signal, the control signal for disabling the first latch for a time period after a transition from the power down mode to the normal operation by preventing a power supply voltage from being provided to the first latch until after the time period.
2. The circuit of claim 1 , wherein the first latch comprises transistors having a lower threshold voltage than transistors that comprise the second latch.
3. The circuit of claim 1 , wherein:
the first latch is characterized as having a first write time; and
the second latch is characterized as having a second write time, wherein the first write time is faster than the second write time.
4. The circuit of claim 1 , wherein the second latch comprises transistors having a lower current leakage than transistors that comprise the first latch.
5. The circuit of claim 1 , wherein the first latch has the power supply voltage removed during the power down mode and restored the time period after the transition from the power down mode to the normal operation.
6. The circuit of claim 1 , wherein:
in the normal operation, the first latch and the second latch alternate between being written and latching in response to a clock signal switching between first and second logic states, respectively; and
the time period is a duration of the first logic state immediately following the transition from the power down mode to the normal operation.
7. The circuit of claim 1 , wherein:
the clock signal has cycles divided into first half cycles and second half cycles, wherein the clock signal is in a first logic state during the first half cycles and in a second logic state during the second half cycles;
the first and second latches receive data present on the data node during the first half cycles and keep the data in a latched condition during the second half cycles; and
the time period is a duration of the first time period immediately following the transition from the power down mode to the normal operation.
8. The circuit of claim 1 , wherein:
the power down control circuit comprises a set/reset latch having a set input for receiving a signal that is active in response to a transition from normal operation to the power down mode, a reset input for receiving the clock signal, and an output; and
the first latch has an input coupled to the output of the set/reset latch.
9. The circuit of claim 8 , further comprising:
an input circuit having an output;
coupling means for coupling, responsive to the clock signal, the output of the input circuit to the data node; and
an output circuit having an input coupled to the data node.
10. The circuit of claim 9 , wherein:
the clock signal has cycles divided into first half cycles and second half cycles, wherein the clock signal is in a first logic state during the first half cycles and in a second logic state during the second half cycles;
the first and second latches receive data present on the data node during the first half cycles and keep the data in a latched condition during the second half cycles;
the reset input is active in response to the first logic state.
11. The circuit of claim 10 , wherein the clock signal is at a beginning of a second half cycle that is extendible when a transition from the power down mode to the normal operation occurs.
12. The circuit of claim 11 , wherein the power down control circuit further comprises a plurality of data nodes having pairs of keeper latches coupled thereto, wherein each pair has one keeper latch for receiving the control signal.
13. A circuit having a normal mode and a power down mode, comprising:
a first input circuit having an output;
a first transmission gate enabled by a clock signal having a first terminal coupled to the output of the first input circuit and a second terminal;
a first latch powered during the normal mode and unpowered during the power down mode having an input/output coupled to the second terminal of the first transmission gate, a clock input for receiving a clock signal, and an enable input for receiving a control signal;
a second transmission gate that is enabled during the normal mode and disabled during the power down mode having a first terminal coupled to the second terminal of the first transmission gate and a second terminal;
a second latch enabled during power down mode and during normal mode having an input/output coupled to the second terminal of the second transmission gate; and
a power down control circuit for providing the control signal to the enable input of the first latch to keep the first latch disabled by preventing a power supply voltage from being provided to the first latch until after a time period after a transition from the power down mode to the normal mode.
14. The circuit of claim 13 , wherein;
the first latch comprises transistors having a first threshold voltage; and
the second latch comprises transistors having second threshold voltage greater than the first threshold voltage.
15. The circuit of claim 13 , wherein;
the first latch has a first write speed; and
the second latch has a second write speed slower than the first write speed.
16. The circuit of claim 13 , wherein:
the first latch comprises transistors characterized as having a first current leakage; and
the second latch comprises transistors characterized as having a second current leakage that is less than the first current leakage.
17. The circuit of claim 13 , further comprising:
a second input circuit having an output;
a third transmission gate enabled by the clock signal having a first terminal coupled to the output of the second input circuit and a second terminal;
a third latch powered during the normal mode and unpowered during the power down mode having an input/output coupled to the second terminal of the third transmission gate and an enable input;
a fourth transmission gate that is enabled during the normal mode and disabled during the power down mode having a first terminal coupled to the second terminal of the third transmission gate and a second terminal; and
a fourth latch enabled during power down mode and during normal mode having an input/output coupled to the second terminal of the fourth transmission gate, wherein:
the power down control circuit provides the power down keep signal coupled to the enable input of the third latch to keep the third latch disabled until after the time period after the transition from the power down mode to the normal mode.
18. In a circuit having a normal mode and a power down mode and having a first latch and a second latch, a method comprising:
writing data into the first latch and the second latch through a data node during a first half cycle of a clock signal that occurs during the normal mode;
latching data from the data node in the first latch and the second latch during a second half cycle of the clock signal that occurs during the normal mode;
disabling the first latch by removing a power supply voltage from the first latch in response to entering the power down mode;
keeping the data latched in the second latch during the power down mode and a time period after a transition from the power down mode to the normal mode; and
enabling the first latch after a time period after the transition from the power down mode to the normal mode by reapplying the power supply voltage to the first latch in response to a control signal, the control signal provided to the first latch after the time period.
19. The method of claim 18 , wherein the step of enabling is further characterized by the time period being the duration of the second half cycle which is extendible after the transition from the power down mode to the normal mode.
20. The method of claim 18 , further comprising:
providing the control signal in response to a power down signal, the power down signal for causing the circuit to transition between the normal mode and the power down mode.