Low voltage low power class A/B output stage
View Patent ↗A CMOS class A/B output stage provides the advantages of high speed operation, low supply voltage requirements, and low quiescent current draw, resulting from the use of subthreshold biasing of the output driver transistors. The architecture of the output stage makes it particularly suitable for use in operational amplifiers in power demanding applications, such as portable instruments, smoke detectors, sensors, or the like.
1. A class A/B amplifier output stage comprising:
a first output driver transistor having a source, a gate, and a drain;
a second output driver transistor having a source, a gate, and a drain, the drain of said first output driver transistor being coupled to the drain of said second output driver transistor;
a first high swing cascode structure coupled to said first output driver transistor and to said second output driver transistor;
a second high swing cascode structure coupled to said first output driver transistor and to said second output driver transistor; and
a voltage source coupled to said first high swing cascode structure, said voltage source providing a minimum operating voltage of about 3VDS sat , where VDS sat is the drain-to-source voltage at saturation for said first output driver transistor and said second output driver transistor, and wherein said first high swing cascode structure and said second high swing cascode structure bias said first output driver transistor to its subthreshold operating region, and bias said second output driver transistor to its subthreshold operating region.
2. A class A/B amplifier output stage according to claim 1 , wherein:
said voltage source provides an operating voltage of VDD, and overdrive voltage for said first and second output driver transistors is about VDD-VT-2VDS sat , where VT is the threshold voltage for said first and second output driver transistors.
3. A class A/B amplifier output stage according to claim 1 , further comprising a biasing architecture coupled to said first high swing cascode structure and said second high swing cascode structure, wherein:
said first high swing cascode structure comprises a first plurality of cascode transistors;
said second high swing cascode structure comprises a second plurality of cascode transistors; and
said biasing architecture biases each of said first plurality of cascode transistors and each of said second plurality of cascode transistors into its respective subthreshold operating region.
4. A class A/B amplifier output stage according to claim 1 , further comprising:
a first current mirror structure coupled to said first high swing cascode structure; and
a second current mirror structure coupled to said second high swing cascode structure.
5. A class A/B amplifier output stage according to claim 4 , wherein:
said first current mirror structure comprises a first current mirror transistor having a source, a gate, and a drain, and a second current mirror transistor having a source, a gate, and a drain, the gate of said first current mirror transistor being coupled to the drain of said second current mirror transistor; and
said second current mirror structure comprises a third current mirror transistor having a source, a gate, and a drain, and a fourth current mirror transistor having a source, a gate, and a drain, the gate of said fourth current mirror transistor being coupled to the drain of said third current mirror transistor.
6. A class A/B amplifier output stage comprising:
a PMOS output driver transistor having a source, a gate, and a drain;
an NMOS output driver transistor having a source, a gate, and a drain, the drain of said PMOS output driver transistor being coupled to the drain of said NMOS output driver transistor;
a first PMOS cascode transistor having a source, a gate, and a drain, the drain of said first PMOS cascode transistor being coupled to the gate of said PMOS output driver transistor;
a first NMOS cascode transistor having a source, a gate, and a drain, the drain of said first NMOS cascode transistor being coupled to the gate of said NMOS output driver transistor;
a final PMOS cascode transistor having a source, a gate, and a drain, the drain of said final PMOS cascode transistor being coupled to the gate of said NMOS output driver transistor;
a final NMOS cascode transistor having a source, a gate, and a drain, the drain of said final NMOS cascode transistor being coupled to the gate of said PMOS output driver transistor;
a first PMOS bias transistor having a source, a gate, and a drain, the gate of said first PMOS bias transistor being coupled to the gate of said first PMOS cascode transistor;
a first NMOS bias transistor having a source, a gate, and a drain, the gate of said first NMOS bias transistor being coupled to the gate of said first NMOS cascode transistor;
a final PMOS bias transistor having a source, a gate, and a drain, the gate of said final PMOS bias transistor being coupled to the gate of said final PMOS cascode transistor, and the drain of said final PMOS bias transistor being coupled to the gate of said first PMOS bias transistor; and
a final NMOS bias transistor having a source, a gate, and a drain, the gate of said final NMOS bias transistor being coupled to the gate of said final NMOS cascode transistor, and the drain of said final NMOS bias transistor being coupled to the gate of said first NMOS bias transistor.
7. The class A/B amplifier output stage of claim 6 , wherein:
the source of said PMOS output driver transistor is coupled to a supply voltage;
the source of said first PMOS cascode transistor is coupled to said supply voltage;
the source of said first PMOS bias transistor is coupled to said supply voltage;
the source of said NMOS output driver transistor is coupled to a ground potential;
the source of said first NMOS cascode transistor is coupled to said ground potential; and
the source of said first NMOS bias transistor is coupled to said ground potential.
8. The class A/B amplifier output stage of claim 6 , wherein the drain of said first PMOS cascode transistor is coupled to the source of said final PMOS cascode transistor; and the drain of said first NMOS cascode transistor is coupled to the source of said final NMOS cascode transistor.
9. The class A/B amplifier output stage of claim 6 , wherein the drain of said first PMOS bias transistor is coupled to the source of said final PMOS bias transistor; and the drain of said first NMOS bias transistor is coupled to the source of said final NMOS bias transistor.
10. The class A/B amplifier output stage of claim 6 , further comprising:
a first current source coupled to said final PMOS bias transistor, said first current source providing a first bias current for said first PMOS bias transistor and for said final PMOS bias transistor; and
a second current source coupled to said final NMOS bias transistor, said second current source providing a second bias current for said first NMOS bias transistor and for said final NMOS bias transistor.
11. The class A/B amplifier output stage according to claim 10 , wherein said first bias current is equal to said second bias current.
12. A class A/B amplifier output stage according to claim 6 , further comprising:
an additional PMOS cascode transistor having a source, a gate, and a drain, the source of said additional PMOS cascode transistor being coupled to the drain of said first PMOS cascode transistor, and the drain of said additional PMOS cascode transistor being coupled to the source of said final PMOS cascode transistor; and
an additional NMOS cascode transistor having a source, a gate, and a drain, the source of said additional NMOS cascode transistor being coupled to the drain of said first NMOS cascode transistor, and the drain of said additional NMOS cascode transistor being coupled to the source of said final NMOS cascode transistor.
13. A class A/B amplifier output stage according to claim 12 , further comprising:
an additional PMOS bias transistor having a source, a gate, and a drain, the source of said additional PMOS bias transistor being coupled to the drain of said first PMOS bias transistor, the gate of said additional PMOS bias transistor being coupled to the gate of said additional PMOS cascode transistor, and the drain of said additional PMOS bias transistor being coupled to the source of said final PMOS bias transistor; and
an additional NMOS bias transistor having a source, a gate, and a drain, the source of said additional NMOS bias transistor being coupled to the drain of said first NMOS bias transistor, the gate of said additional NMOS bias transistor being coupled to the gate of said additional NMOS cascode transistor, and the drain of said additional NMOS bias transistor being coupled to the source of said final NMOS bias transistor.
14. An electronic circuit comprising:
a first output driver transistor having a source, a gate, and a drain;
a second output driver transistor having a source, a gate, and a drain, the drain of said first output driver transistor being coupled to the drain of said second output driver transistor;
a first cascode transistor having a source, a gate, and a drain, the drain of said first cascode transistor being coupled to the gate of said second output driver transistor;
a second cascode transistor having a source, a gate, and a drain, the drain of said second cascode transistor being coupled to the gate of said first output driver transistor;
a first bias transistor having a source, a gate, and a drain, the gate of said first bias transistor being coupled to the gate of said first cascode transistor;
a second bias transistor having a source, a gate, and a drain, the gate of said second bias transistor being coupled to the gate of said second cascode transistor, and the drain of said second bias transistor being coupled to the gate of said first bias transistor; and
a differential transistor pair having a common source node coupled to a current source, a first gate node for a first polarity component of an input signal, a second gate node for a second polarity component of said input signal, a first drain node, and a second drain node coupled to the drain of said second bias transistor.
15. The electronic circuit of claim 14 , further comprising:
a third cascode transistor having a source, a gate, and a drain, the drain of said third cascode transistor being coupled to the gate of said first output driver transistor; and
a fourth cascode transistor having a source, a gate, and a drain, the drain of said fourth cascode transistor being coupled to the gate of said second output driver transistor.
16. The electronic circuit of claim 15 , further comprising:
a third bias transistor having a source, a gate, and a drain, the gate of said third bias transistor being coupled to the gate of said third cascode transistor; and
a fourth bias transistor having a source, a gate, and a drain, the gate of said fourth bias transistor being coupled to the gate of said fourth cascode transistor, and the drain of said fourth bias transistor being coupled to the gate of said third bias transistor.
17. The electronic circuit of claim 16 , wherein said first output driver transistor, said third cascode transistor, said fourth cascode transistor, said third bias transistor, and said fourth bias transistor are NMOS transistors; and said second output driver transistor, said first cascode transistor, said second cascode transistor, said first bias transistor, and said second bias transistor are NMOS transistors.
18. The electronic circuit of claim 17 , wherein said differential transistor pair comprises:
a first PMOS input transistor having a source, a gate, and a drain; and
a second PMOS input transistor having a source, a gate, and a drain; wherein
the source of said first PMOS input transistor and the source of said second PMOS input transistor are coupled to said common source node;
the gate of said first PMOS input transistor corresponds to said first gate node;
the gate of said second PMOS input transistor corresponds to said second gate node;
the drain of said first PMOS input transistor corresponds to said first drain node; and
the drain of said second PMOS input transistor corresponds to said second drain node.
19. The electronic circuit of claim 14 , wherein said electronic circuit comprises an operational amplifier; and
said electronic circuit further comprises an output node coupled to the drain of said first output driver transistor and coupled to the drain of said second output driver transistor.