Built-in self-calibration (BISC) technique for regulation circuits used in non-volatile memory
View Patent ↗A reference voltage regulation circuit ( 143 ) is provided in which one or more input voltage signals (Vref, Vref′) are selectively coupled to a configurable amplifier ( 114 ) which is coupled through a sample and hold circuit ( 120 ) to a voltage follower circuit ( 122 ) which is coupled in feedback to the configurable amplifier ( 114 ) for generating an adjusted output voltage at a circuit output ( 130 ), where the voltage follow circuit comprises a resistor divider circuit ( 126 ) that is controlled by a calibration signal (Cal<n:0>) generated by a counter circuit ( 128 ) selectively coupled to the output of the configurable amplifier when configured as a comparator for generating the calibration signal in response to a clock signal, where the calibration signal represents a voltage error component (Verror, Voffset) that is removed from the circuit output when the calibration signal is applied to the resistor divider circuit during normal operational.
1. A reference voltage regulation circuit, comprising:
an input switch for receiving one or more input voltage signals;
a configurable amplifier coupled to the input switch, where the configurable amplifier may be configured to operate as an operational amplifier or as a comparator;
a sample and hold circuit coupled to an output of the configurable amplifier;
a voltage follower circuit coupled in feedback between the sample and hold circuit and the configurable amplifier for generating an adjusted output voltage at a circuit output, where the voltage follow circuit comprises a resistor divider circuit that is controlled by a calibration signal; and
a counter circuit selectively coupled to the output of the configurable amplifier when configured as a comparator for generating the calibration signal in response to a clock signal, where the calibration signal represents a voltage error component that is removed from the circuit output when the calibration signal is applied to the resistor divider circuit during normal operational.
2. The reference voltage regulation circuit of claim 1 , where the input switch comprises a first input switch for coupling either an external reference voltage or a test reference voltage to a positive input terminal of the configurable amplifier.
3. The reference voltage regulation circuit of claim 2 , where the configurable amplifier is configured to operate as an operational amplifier whenever the external reference voltage is coupled to the positive input terminal of the configurable amplifier and where the voltage follower circuit is connected through the sample and hold circuit to the configurable amplifier to generate an output voltage at the circuit output during a sampling phase.
4. The reference voltage regulation circuit of claim 2 , where the configurable amplifier is configured to operate as a comparator whenever the test reference voltage is coupled to the positive input terminal of the configurable amplifier and where the counter circuit is controlled by the output of the comparator to generate the calibration signal in response to a clock signal during a measuring phase.
5. The reference voltage regulation circuit of claim 2 , where the counter circuit generates during a measuring phase a calibration signal substantially representing a negative of the voltage error component that is present in the external reference voltage by counting a digital value during a measuring phase that is substantially equal to the voltage error component and then inverting the digital value to generate the calibration signal that is applied to the resistor divider circuit during normal operation.
6. The reference voltage regulation circuit of claim 1 , where the input switch comprises a dual mode input switch for providing first and second switch configurations, where the first switch configuration connects a test reference input voltage to a positive input terminal of the configurable amplifier and connects the resistor divider circuit to a negative input terminal of the configurable amplifier, while second switch configuration connects the test reference input voltage to the negative input terminal of the configurable amplifier and connects the resistor divider circuit to the positive input terminal of the configurable amplifier.
7. The reference voltage regulation circuit of claim 6 , where the configurable amplifier is configured to operate as an operational amplifier whenever the test reference input voltage and an op amp offset voltage are coupled to the positive input terminal of the configurable amplifier and where the voltage follower circuit is connected through the sample and hold circuit to the configurable amplifier to generate an output voltage at the circuit output during a sampling phase.
8. The reference voltage regulation circuit of claim 6 , where the configurable amplifier is configured to operate as a comparator whenever the test reference input voltage is coupled to the negative input terminal of the configurable amplifier and where the counter circuit is controlled by the output of the comparator to generate the calibration signal in response to a clock signal during a cancel phase.
9. The reference voltage regulation circuit of claim 6 , where the counter circuit generates during a cancel phase a calibration signal substantially representing a negative of the voltage error component that is present as an opamp offset component in the configurable amplifier by counting a digital value during the cancel phase that is substantially equal to twice the opamp offset component and then inverting and dividing the digital value by two to generate the calibration signal that is applied to the resistor divider circuit during normal operation.
10. A method for generating a calibrated reference voltage, comprising:
sampling and holding a reference voltage generated by an operational amplifier comprising an opamp output, a positive opamp input for receiving an internal reference voltage and a negative opamp input for receiving in feedback the reference voltage generated by the opamp output;
measuring an error voltage component included in the reference voltage with an analog-to-digital converter circuit which compares the reference voltage with a desired reference voltage to generate a first digital calibration signal representing a value substantially equal to the error voltage component;
inverting the first digital calibration signal to generate a second digital calibration signal representing a value substantially equal to a negative of the error voltage component;
applying the second digital calibration signal to a resistor tap circuit connected in feedback between the opamp output and the negative opamp input to subtract the value substantially equal to the voltage error component from the opamp output.
11. The method claim 10 , where sampling and holding the reference voltage comprises:
connecting an internal reference voltage to the positive opamp input and connecting a voltage follower circuit between the opamp output and the negative opamp input;
sampling the opamp output with a sample and hold circuit which is configured to sample an opamp output value; and
capturing the opamp output with a sample and hold circuit which is configured to hold the opamp output value.
12. The method claim 10 , where measuring the error voltage component comprises:
connecting the desired reference voltage to the positive opamp input;
disabling frequency response compensation in the operational amplifier;
setting a counter circuit to a known state;
connecting the opamp output to the counter circuit; and
generating the first digital calibration signal from the counter circuit in response to a clock signal.
13. The method claim 10 , where inverting the first digital calibration signal comprises performing a one's complement on the first digital calibration signal to generate the second digital calibration signal.
14. The method claim 10 , where applying the second digital calibration signal to the resistor tap circuit comprises:
connecting the internal reference voltage to the positive opamp input;
enabling frequency response compensation in the operational amplifier;
applying the second digital calibration signal to the resistor tap circuit connected in feedback between the opamp output and the negative opamp input to subtract the value substantially equal to the voltage error component from the opamp output; and
sampling the opamp output with a sample and hold circuit which is configured to sample an opamp output value which is substantially the desired reference voltage.
15. The method claim 10 , further comprising storing the second digital calibration signal in memory.
16. A method for generating a reference voltage, comprising:
sampling and holding a reference voltage generated by an operational amplifier comprising an opamp output, a positive opamp input for receiving a desired reference voltage and a negative opamp input for receiving in feedback the reference voltage generated by the opamp output;
measuring an offset voltage component included in the reference voltage with an analog-to-digital converter circuit which compares the reference voltage with a desired reference voltage to generate a first digital calibration signal representing a value substantially equal to twice the offset voltage component;
inverting and dividing by two the first digital calibration signal to generate a second digital calibration signal representing a value substantially equal to a negative of the offset voltage component;
applying the second digital calibration signal to a resistor tap circuit connected in feedback between the opamp output and the negative opamp input to subtract the value substantially equal to the offset voltage component from the opamp output.
17. The method claim 16 , where sampling and holding the reference voltage comprises:
connecting the desired reference voltage to the positive opamp input and connecting a voltage follower circuit between the opamp output and the negative opamp input;
sampling the opamp output with a sample and hold circuit which is configured to sample an opamp output value; and
capturing the opamp output with a sample and hold circuit which is configured to hold the opamp output value.
18. The method claim 16 , where measuring the offset voltage component comprises:
connecting the desired reference voltage to the negative opamp input and connecting the voltage follower circuit between the opamp output and the positive opamp input;
disabling frequency response compensation in the operational amplifier;
setting a counter circuit to a known state;
connecting the opamp output to the counter circuit; and
generating the first digital calibration signal from the counter circuit in response to a clock signal.
19. The method claim 16 , where inverting and dividing by two the first digital calibration signal comprises performing a one's complement on the first digital calibration signal to generate an intermediate value, and right-shifting the intermediate value to generate the second digital calibration signal.
20. The method claim 16 , where applying the second digital calibration signal to the resistor tap circuit comprises:
connecting the desired reference voltage to the positive opamp input and connecting the voltage follower circuit between the opamp output and the negative opamp input;
enabling frequency response compensation in the operational amplifier;
applying the second digital calibration signal to the resistor tap circuit connected in feedback between the opamp output and the negative opamp input to subtract the value substantially equal to the offset voltage component from the opamp output; and
sampling the opamp output with a sample and hold circuit which is configured to sample an opamp output value which is substantially the desired reference voltage.