III-V MOSFET fabrication and device
View Patent ↗A semiconductor fabrication process includes forming a gate dielectric layer ( 120 ) overlying a substrate ( 101 ) that includes a III-V semiconductor compound. The gate dielectric layer is patterned to produce a gate dielectric structure ( 121 ) that has a substantially vertical sidewall ( 127 ), e.g., a slope of approximately 45° to 90°. A metal contact structure ( 130 ) is formed overlying the wafer substrate. The contact structure is laterally displaced from the gate dielectric structure sufficiently to define a gap ( 133 ) between the two. The wafer ( 100 ) is heat treated, which causes migration of at least one of the metal elements to form an alloy region ( 137 ) in the underlying wafer substrate. The alloy region underlies the contact structure and extends across all or a portion of the wafer substrate underlying the gap. An insulative or dielectric capping layer ( 140,150 ) is then formed overlying the wafer and covering the portion of the substrate exposed by the gap.
1. A semiconductor fabrication process, comprising:
forming, using molecular beam epitaxy, a gate dielectric layer overlying a wafer substrate, wherein the substrate includes at least one layer of a III-V semiconductor compound and wherein the gate dielectric layer includes a compound comprising an oxygen element and a second element wherein the second element is present in the III-V semiconductor compound;
patterning the gate dielectric layer to produce a gate dielectric structure having a substantially vertical sidewall;
forming a contact structure overlying said wafer substrate and laterally displaced from the gate dielectric structure, wherein the contact structure comprises at least one metal and wherein a lateral separation between the contact structure and the gate dielectric structure defines a gap;
heat treating the contact structure to produce an alloy region within the semiconductor substrate, wherein the alloy region underlies the contact structure and extends across a portion of the wafer substrate underlying the gap; and
forming a capping layer overlying the wafer.
2. The method of claim 1 , wherein patterning the gate dielectric layer comprises:
forming a polymethyl methylcrylate (PMMA) mask overlying a first portion of the gate dielectric and exposing a second portion of the gate dielectric layer; and
removing the second portion of the gate dielectric layer by immersing the wafer in a highly dilute HCl solution.
3. The method of claim 1 , wherein the substantially vertical sidewall forms an angle in the range of approximately 45° to 90° with the underlying substrate.
4. The method of claim 1 , wherein contact structure has a work function exceeding approximately 5 eV.
5. The method of claim 1 , wherein forming the contact structure includes forming at least one material selected from Ni, Ge, and Au.
6. The method of claim 1 , wherein said heat treating comprises performing a rapid thermal anneal by subjecting the wafer to an ambient of approximately 440° C. for a duration of approximately 30 seconds.
7. The method of claim 1 , wherein forming the capping layer comprises:
forming a first capping layer of a silicon-nitrogen compound; and
depositing a second capping layer of a silicon-nitrogen compound overlying the first capping layer.
8. The method of claim 7 , wherein forming the first capping layer comprises forming the first capping layer using a room temperature deposition process.
9. The method of claim 7 , wherein depositing the second capping layer comprises forming the second capping layer by chemical vapor deposition at a temperature of approximately 200° or less.
10. The method of claim 1 , further comprising forming an epitaxial layered structure overlying the wafer substrate and wherein said forming of said gate dielectric comprises forming said gate dielectric overlying said epitaxial layered structure.
11. A method for fabricating a III-V MOSFET, comprising:
forming a compound semiconductor layer overlying a wafer substrate;
forming a gate dielectric layer overlying the compound semiconductor layer;
patterning the gate dielectric layer to produce a gate dielectric structure;
forming a contact structure comprising at least one metal element, the contact structure overlying the compound semiconductor layer and being laterally displaced from the gate dielectric structure sufficiently to define a gap between the contact structure and the gate dielectric structure;
forming an alloy region within the compound semiconductor layer by exposing the wafer to a heated ambient for a specified duration, wherein the alloy region includes at least some of the metal element and wherein the alloy region extends laterally through at least a portion of the compound semiconductor layer underlying the gap; and
forming an insulating film overlying the wafer, wherein a lower surface of the insulating film is in contact with a portion of an upper surface of the compound semiconductor layer exposed by the gap;
wherein forming the insulating film comprises:
depositing, at a temperature of less than approximately 30° C., a first capping layer film of a first silicon nitrogen compound; and
depositing, using chemical vapor deposition at a temperature of less than approximately 200° C., a second capping layer film of a second silicon-nitrogen compound.
12. The method of claim 11 , wherein patterning the gate dielectric layer comprises patterning the gate dielectric layer to produce a gate dielectric structure having a substantially vertical sidewall.
13. The method of claim 11 , wherein patterning the gate dielectric layer comprises:
depositing a film of polymethyl methylcrylate (PMMA) overlying the gate dielectric;
exposing portions the PMMA film to radiation;
removing exposed portions of the PMMA film to expose portions of the gate dielectric layer; and
removing exposed portions of the gate dielectric layer by immersion in a highly dilute solution of HCl.